A pairwise substitutional fault tolerance technique for the cube-connected cycles architecture

The construction of computer systems containing integrated circuit logic components with very large scale integration (VLSI), that is, many thousands of gates, is inevitable. Such levels of integration have already been achieved in memory components. There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.

Preparata and Vuillemin proposed the cubeconnected cycles (CCC) in 1981 [lS], and in the same paper, gave an asymptotically-optimal layout scheme for the CCC. We give a new layout scheme for the CCC which requires less than half of the area of th,e Preparata- Vuillemin layout. We also give a non-trivial lower bound on the layout area of the CCC. There is a constant factor of 2 between the new layout and the lower bound. We conjectur.e that the new layout is optimal (minimal).

: This report describes techniques for very large scale integration (VLSI) implementation of arithmetic algorithms. The report describes an algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root. Keywords include: Very large scale integration (VLSI); and Floating point chip design.

Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: (1) nearly invisible to human and machine inspection; (2) difficult to remove; and (3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that the placement and routing applications considered in our methods achieve strong proofs of authorship and are resistant to tampering and do not adversely influence timing.

Fault tolerant design is a technique emerging in Integrated Circuits (ICs) to deal with the increasing error susceptibility (Soft Errors, Single Event Upsets, (SEUs)) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects, thereby increasing the yield and lowering the production cost in certain conditions. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques for SEUs) leads to a synergistic advantage under certain conditions: lower production costs because of a better yield. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular designs are presented as function of IC area, fault tolerant overhead and defect density.

Although sorting networks have extensively been reported in literature (Batcher, 1962), there are a few references that cover a detailed explanation about their VLSI (Very Large Scale of Integration) realization in CMOS (Complementary Metal-Oxide-Semiconductor) technology (Turan et al., 2003). From an algorithmic point of view, a sorting network is defined as a sequence of compare and interchange operations depending only on the number of elements to be sorted. From a hardware perspective, sorting networks can be visualized as combinatorial circuits where a set of denoted compare-swap (CS) circuits can be connected in accordance to a specific network topology (Knuth, 1997). In this chapter, the design of sorting networks in CMOS technology with applicability to VLSI design is approached at block, transistor, and layout levels. Special attention has been placed to show the hierarchical structure observed in sorting schemes where the so called CS circuit constitutes the fundamental standard cell. The CS circuit is characterized through SPICE simulation making a particular emphasis in the silicon area and delay time parameters. In order to illustrate the inclusion of sorting networks into specific applications, like signal processing and nonlinear function evaluation, two already reported examples of integrated circuit designs are provided (Agustin et al., 2011; Jimenez et al., 2011).

This paper describes the successful development and demonstration of a Laser Fault Injection (LFI) technique to inject soft, i.e., transient, faults into VLSI circuits in a precisely-controlled, non-destructive, non-intrusive manner for the purpose of validating fault tolerant design and performance. The technique described in this paper not only enables the validation of fault-tolerant VLSI designs, but it also offers the potential for performing automated testing of board-level and system-level fault tolerant designs including fault tolerant operating system and application software. The paper describes the results of LFI testing performed to date on test metal circuit structures, i.e., ring oscillators, flip-flops, and multiplier chains, and on an advanced RISC processor, with comprehensive on-chip concurrent error detection and instruction retry, in a working single board computer. Relative to rapid, low cost testing and validation of complex fault tolerant designs, with the automated laser system at the Laser Restructuring Facility at the University of South Florida Center for Microelectronics Research (USF/CMR), a design with 10000 test points could be tested and validated in under 17 minutes. In addition to describing the successful demonstration of the technique to date, the paper discusses some of the challenges that still need to be addressed to make the technique a truly practical fault tolerant design validation tool.

Process quality and delivery time have received increasing attention in the highly competitive electronics industry. Many studies have proposed process capability indices (PCIs) to assess process effectiveness. However, methods to assess the performance in terms of processing and delivery times of products have seldom been discussed. The conventional PCIs can no longer assess the processing time (PT) and delivery time (DT) performance objectively or identify the relationship between PCIs and the non-conformance rate of PT or the conformance rate of DT. Lacking an effective performance index or an objective testing procedure to assess process/product performance will lead to inefficiency or a high manufacturing management overhead cost. Therefore, this study offers effective performance indices (i.e., PCIs) to assess the PT and DT performance for very large scale integration (VLSI). The uniformly minimum variance unbiased (UMVU) estimators of the proposed PCIs are derived under the assumption of a normal process distribution. The PCI estimators are then employed to construct a one-to-one relationship between the PCIs and the conformance rate of DT or non-conformance rate of PT, respectively. Finally, hypothesis testing procedures for the proposed PCIs are also developed. The testing procedure can be used to determine whether DT or PT can satisfy a customer’s requirements.

Very large scale Integration (VLSI) was used to create hardware which initiates by the explanation of algorithm as well as employs computer program. In digital systems, multiplier and adder are the fundamental components in design of integrated circuit applications. High speed devices play an essential role in VLSI applications. Adder enhancement is used in miscellaneous application in new VLSI system like multiplier design, ALU and etc. An efficient adder circuit design is used to optimize various metrics. But, design complexity was not reduced by existing VLSI design. To handle such limitations, Deep Fully Connectedness Convolutional Broken Stick Regressive Brent-Kung Adder Enhancement (DFCCBSRBKAE) Technique is introduced in VLSI circuits. Input layer, two hidden layers as well as output layer comprises four layer of DFCCBSRBKAE Technique. The carry inputs are transferred to input layer. Input data is transferred to hidden layer 1. Broken-stick regression analysis is performed for pre-processing data. Next, pre-processed data is transferred to hidden layer 2. Carry generation and post-processing is carried out in hidden layer 2 and the output results are covered by the convolution. At last, outcomes were attained within output layer. This in turn helps to perform an efficient adder enhancement of digital multiplier with minimal power and time consumption. The performance of DFCCBSRBKAE Technique is determined by power and time consumption. DFCCBSRBKAE Technique reduces the area, speed, and delay and power consumption of adder enhancement compared with conventional methods.

In this paper, a new version of very large scale integration (VLSI) layouts compaction problem is considered. Bar visibility graph (BVG) is a simple geometric model for VLSI chip design and layout problems. In all previous works, vertical bars or other chip components in the plane model gates, as well as edges, are modeled by horizontal visibilities between bars. In this study, for a given set of vertical bars, the edges can be modeled with orthogonal paths known as staircases. Therefore, we consider a new version of bar visibility graphs (BsVG). We then present an algorithm to solve the s-visibility problem of vertical segments, which can be implemented on a VLSI chip. Our algorithm determines all the pairs of segments that are s-visible from each other.

The fast-moving telecommunications industry is driving the demand for Very Large Scale Integration (VLSI) design approaches that can achieve higher performance at lower power consumption and higher reliability. This paper presents enhanced VLSI design methodologies tailored for telecommunications systems, with an emphasis on key performance metrics optimization, such as speed, power efficiency, and scalability. The new strategies presented incorporate novel design paradigms including power-aware architectures, adaptive clocking mechanisms, and high-density integration techniques. Additionally, deep sub-micron technology has brought with it a whole new set of challenges, such as increased leakage currents and signal integrity problems, which are mitigated through novel circuit-level techniques and layout optimizations. One of the major focuses in the research is hardware integration, especially the accelerators needed for specialized functions in telecommunications: signal processing and encryption. Next, design methodologies supported by innovative CAD tools and simulation environments have been discussed; this helps increase design efficiency as well as helps reduce time-to-market. To that end, low-power techniques such as multi-threshold voltage and power gating have been focused on in relation to the design of energy-efficient hardware for telecommunications. This paper demonstrates, through simulation results and case studies, that the proposed VLSI strategies can improve system performance significantly while maintaining power efficiency and low cost. The findings contribute to the ongoing research and development in VLSI technology and offer a roadmap for designing next-generation telecommunications systems capable of supporting emerging applications such as 5G, IoT, and beyond. These strategies not only enhance the robustness of the design but also open the way toward more scalable and adaptive telecommunications infrastructures

Embedding a graph in a book is an arrangement of vertices in a line along the spine of the book and edges on the pages in such a way that edges residing on the same page do not cross. Each graph has many different embeddings in books. The embedding with the minimum number of pages is optimum. This paper is a survey of problems dealing with embedding graphs in books. The computational complexity of the problems is mentioned. Some examples of optimum graph embeddings in books are presented. The problem of embedding a graph in a book is very important from the technical point of view. Optimisation of graph embeddings may be important in several technical applications, e.g. sorting with parallel stacks, fault-tolerant processor arrays design, and layout problems with application to very large scale integration (VLSI).

As the demand for artificial intelligence continues to grow, there is a need for specialized hardware that can efficiently process and power AI algorithms. This is where VLSI (Very Large-Scale Integration) design comes into play. By integrating millions, or even billions, of transistors onto a single chip, VLSI design enables the creation of powerful AI-integrated circuits. However, designing hardware specifically for artificial intelligence poses its own set of challenges. The complexity of AI algorithms and the need for parallel processing capabilities demand innovative solutions. VLSI designers must carefully consider factors such as power consumption, heat dissipation, and the integration of specialized neural network accelerators. In addition to these considerations, VLSI designers must also address the scaling limitations of semiconductor technology. As AI algorithms become more complex, the demand for advanced VLSI architecture increases. Designers must find ways to enhance transistor density and performance while overcoming the limitations imposed by the physical laws governing semiconductor manufacturing. In-Memory Computing (IMC) is an emerging paradigm designed to overcome the limitations of the traditional Von Neumann architecture, particularly for energy-efficient AI applications. Traditional computing systems suffer from the "memory wall"—a bottleneck caused by the constant transfer of data between the CPU and memory. This leads to inefficiencies in latency, bandwidth, and energy consumption, especially for AI tasks which involve huge volumes of matrix operations and data movement. Keywords: Very Large-Scale Integration (VLSI), Artificial Intelligence (AI), In-memory computing (IMC), Neuromorphic, multiply-and-accumulate (MAC), RRAM (Resistive RAM), MRAM (Magnetoresistive RAM), PCM (Phase-Change Memory), FeFET (Ferroelectric FET), spiking neural networks (SNNs)

In the last forty years the semiconductor industry focused on the downscaling process of the CMOS (Complementary Metal-Oxide-Semiconductor) technology, trying to follow as much as possible the empirical Moore's Law. In the last five years this trend has been facing technology limits that have led to the development of a new research field, named Beyond CMOS, which investigates new electron devices concept and materials that can replace or co-integrate the standard technology, to make large scale integrated (LSI), high performance, low power devices. Carbon nanotubes (CNTs) are considered one of the most promising materials for Beyond CMOS devices, both at front-end and back-end level. The development of the research on this new organic material is due to its nanometer scale dimensions and to its outstanding electrical (metallic and semiconducting behavior, ballistic conduction, current density > 109 A/cm2) and mechanical (Young's modulus ∼1 TPa) properties, nevertheless due to its low mass (mass density ρ = 1300 kg/m3). Among the several CNT applications already reported in literature (interconnections, sensors, transistors, memory, etc.), a particular interest is on their use to build Nano-Electro-Mechanical (NEM) devices, such as resonators and switches. NEM relays based on carbon nanotubes show large-current density drive and high speed operation compared to metal-based NEMS counterparts, low actuation voltage and low power, performances which are promising for radio-frequency (RF) applications, where RF MEM devices are considered as replacement solution for their off-chip and/or solid-state counterparts in front-end transceivers. Most of the previously reported CNT NEM switches concerns relay configuration based on one single movable nanotube and its DC characterization. Despite individual proof-of-concept merits, an electromechanical switch based on a single CNT usually presents an output signal level that is too low for practical applications and a poor reliable fabrication process, which opposes the precise control at wafer level achieved by standard technology. Alternatively, a very large-scale integration of NEM devices requires the exploitation of high-density aligned arrays of nanotubes, grown in precise locations and that could be patterned into well-defined and controlled configurations. The objective of this research work was to develop LSI NEM switches based on high dense carbon nanotube arrays in the back end of the line (BEOL), with conductive and capacitive contacts and tested from DC up to high frequency (RF), in order to evaluate their performances in a wide range of operations. The synthesis process of carbon nanotubes was performed by thermal CVD and temperature, gas concentration and catalyst pretreatment were optimized to achieve high dense aligned CNT arrays. A study on the catalyst geometries and on the substrate materials were performed in order to obtain horizontal aligned arrays grown directly on metallic substrate without density change. We developed a novel surface micromachining process to suspend CNT arrays. The DC characterization of CNT NEM switches was exploited to extract the equivalent electromechanical properties of the CNT membranes, since they behave as a new body material. We extracted an equivalent flexural modulus of 8.5 GPa and a resistivity of 0.0077 Ωcm. The devices, in both configurations, present a very low actuation voltage, below 10 V, lower than typical metal NEM switch for the same dimensions and a comparable switching time. The RF characterization was performed in the telecommunication frequency range (up to 6 GHz) showing reasonably high isolation and low insertion loss. The relay shows a lower reliability than the capacitive switch, due to the elevated drive current which induces the CNTs burning at the metal-to-metal interface. The RF measurements were used to extract the parameters of the proposed devices equivalent lumped model. Several implementations of CNT NEM switches, both for DC (reconfigurable interconnects, logic functions, memories) and RF (signal routing purposes in RF system Front-Ends, phase shifting networks or digitalized capacitor banks) applications, were reported.

The revolution of energy management in Very Large Scale Integration (VLSI) can be realized for lower power and sustainability with Artificial Intelligence (AI) and Machine Learning (ML) as an essential tool to maintain the smart city. Reduction of size is the origin of very-scale integrated (VLSI) technology that permits as usual more complex circuit building and also achieves higher densities in electronics systems. AI and ML machines optimize the performance of these systems resulting in a higher clean energy yield, solving for some or all supporting smart cities with equitable access is touted to be achieved. This chapter focuses on minimizing energy waste, predicting maintenance intervals for critical infrastructures, integrating into smart grids and a more robust renewable energy generation - these are the building blocks of smarter cities that will consume fewer resources while generating increasingly efficient services.