A parallel multiple hashing architecture for IP address lookup

An efficient IP address lookup algorithm based on a small balanced tree using entry reduction

Continuing growth in traffic, the size of routing table as well as the link speeds puts great challenge on the performance of Internet address lookup. The packet forwarding engine need perform 150 million IP address lookups per second for a 100Gbps line card while accommodating up to 500,000 prefixes and very likely 1M in the near future. TCAM based lookup solutions do not scale well for the next-generation due to its high power dissipation and large footprint. Algorithmic solutions can achieve high throughputs with hardware parallelism and compact storage needs, but can hardly scale simultaneously in the three dimensions of increased table size, throughput, and prefix length as IP moves to 64 bit IPv6 addresses. We propose a novel IPv6 lookup algorithm called Prefix Range Based Binary Search (PRB-BS) using binary search over hash tables organized by the range of prefix length. By eliminating the path information of the subtrie our scheme reduces the memory demands considerably. Besides, the binary search scheme based on prefix range reduces the worst case time of hash lookups to log2L, with L being the number of subtrie layers. We also introduce asymmetry binary search to further reduce memory demands and memory accesses. Compared with the tree bitmap algorithm widely used by many modern routers the memory requirements of PRB-BS algorithm is about 55% of the tree bitmap algorithm. The experiment results also show that the average search depth of PRB-BS algorithm is stable at 2 with the increased number of prefixes, which reflects better scalability of PRB-BS algorithm.

IP 주소 검색은 라우터에서 가장 중요하고 복잡한 기능중 하나이다. 본 논문에서는 고성능 라우터에서 IP 주소 검색의 성능을 향상시키기 위해 LC-trie를 개선하는 기법을 제안한다. TCAM(Ternary Content Addressable Memory)에서 테이블 압축을 위해 이용한 프리픽스 pruning 방법을 LC-trie에 효과적으로 적용한다. 이러한 기법은 메모리 참조 횟수를 감소시키고 검색의 속도를 높일 수 있다. 또한, 실제 사용되는 포워딩 테이블과 트래픽 분포를 사용하여 검색 시간과 메모리 참조 횟수 둥의 관점에서 개선된 기법의 성능을 기존의 LC-trie 기법과 비교 평가한다. IP address lookup is one of the most important and complex functions in the router. In this paper, we propose an improved technique of LC-trie to increase the performance of IP address lookup in the high performance router. We effectively apply the prefix pruning method, which is used for the compression of the forwarding table in TCAM((Ternary Content Addressable Memory), to the LC-trie. This technique can decrease the number of memory accesses and upgrade the lookup speed. Moreover, through the real forwarding table and the real traffic distribution, we evaluate the performance of our scheme in terms of the lookup time and the number of memory access, comparing with that of the previous LC-trie.

As data rates in the Internet increase, the Internet Protocol (IP) address lookup is required to be resolved in shorter resolution times. IP address lookup involves finding the longest matching prefix from a database of prefixes that better matches the destination address of a packet. The fastest IP-address lookup solutions are based on ternary content addressable memories (TCAMs), which can resolve the IP lookup in one memory-access time. However, TCAMs have a high power consumption and large complexity that may limit their scalability and storage capacity. An alternative is to use random access memory (RAM) that stores a forwarding table in a trie form. Proposed trie-based solutions for IP lookup require three or more memory-access times in the worst-case scenario. This makes them unattractive despite their reduced power consumption. In this paper, we propose a flexible and fast trie-based IP-lookup algorithm where parallel searching is performed. This algorithm performs lookup in two memory- access times whith a feasible amount of memory or three memory access times with reduced memory.

In this paper, we proposed a parallel IP address lookup architecture, which is a novel concept based on graphics processing unit (GPU) via Compute Unified Device Architecture (CUDA). Device function in GPU only performs IP address lookup. Host function is exploited to construct and update the data structure of IP address lookup. Both host and device functions can be executed simultaneously to fully utilize computation resource. Accordingly, we propose an IPv6-capable data structure and implement the data structure with CUDA. One of experimental results shows that G92 GPU can achieve a throughput more than 1.3 billion packets per second (GPPS) on IPv4 routing tables with more than 350K prefixes, which signifies CUDA-based IP forwarding engine with the proposed approach has the capability of GPPS IP forwarding rate on a low-end CUDA device. By employing dual data structures, our implementation can support several hundred thousand updates per second. Furthermore, the proposed forwarding scheme is varied to be applied and compatible with other Internet schemes and devices.

The conventional Deep Neural Networks (DNNs) accelerator is usually designed based on array-based processing element computing. By using the array-based computation, memory access can be reduced efficiently based on a specific dataflow. However, the computing flexibility of the contemporary DNN accelerators is usually restricted because they support the monotonous computing dataflow. Hence, the computing efficiency will be degraded under the different hyperparameters of the target DNN (e.g., kernel size, layers, etc.) Because of the high flexibility and scalability of Network on Chip (NoC) interconnection, the NoC-based DNN design methodology becomes an attractive design paradigm, which reduces the design complexity of the DNN accelerator implementation. However, the current NoC-based DNN designs usually assume that the entire DNN model can be mapped to the target NoC. In this way, the area overhead will be larger with respect to the increasing DNN scale. To solve this problem, we propose a dynamic mapping algorithm, called: dense mapping. The dense mapping is used to map the neuron operations to the NoC as long as the available computing resources are enough for the neuron operations. Besides, an input sharing mechanism is proposed to reuse input data. In this way, we can not only process a DNN model on a small-scale NoC but also decrease the number of memory access by using the proposed input sharing mechanism. Compared with the related work, the proposed approaches help to reduce 60.5% number of memory access and improve 96.5% throughput due to fewer memory accesses.

IP address lookup operation determines the longest prefix matching each incoming destination address. As a fundamental operation for packet forwarding at Internet routers, search speed for routing table lookup is the most important performance metric. Previous researches have shown that the search performance of trie-based algorithms can be improved by adding on-chip Bloom filters. In these algorithms, an on-chip Bloom filter identifies the membership of a node in an off-chip trie, and the number of trie accesses is reduced, because the Bloom filter can filter out accesses to non-existing nodes in the trie. In this paper, we propose a new method of utilizing a Bloom filter for the IP address lookup problem. In the previous Bloom filter-based approach, false positiveness has to be identified by accessing the off-chip trie for every positive result, since false positives can produce wrong results. In our proposed approach, the false positiveness of a Bloom filter is not necessarily identified by making false positives not mislead the search. Hence the number of off-chip trie accesses are significantly reduced. Simulation results show that the best matching prefix can be found with a single off-chip access in average and in the worst-case with the reasonable size of a Bloom filter in our proposed method.

The IP address lookup problem is one of the major bottlenecks in high performance routers. Previous solutions to this problem first describe it in the general terms of longest prefix matching and, then, are experimented on real routing tables T. In this paper, we follow the opposite direction. We start out from the experimental analysis of real data and, based upon our findings, we provide a new and simple solution to the IP address lookup problem. More precisely, our solution for m-bit IP addresses is a reasonable trade-off between performing a binary search on T with O(log |T|) accesses, where |T| is the number of entries in T, and executing a single access on a table of 2m entries obtained by fully expanding T. While the previous results start out from space-efficient data structures and aim at lowering the O(log |T|) access cost, we start out from the expanded table with 2m entries and aim at compressing it without an excessive increase in the number of accesses. Our algorithm takes exactly three memory accesses and occupies O(2m/2 + |T|2) space in the worst case. Experiments on real routing tables for m = 32 show that the space bound is overly pessimistic. Our solution occupies approximately one megabyte for the MaeEast routing table (which has |T| ? 44; 000 and requires approximately 250 KB) and, thus, takes three cache accesses on any processor with 1 MB of L2 cache. According to the measurement obtained by the VTune tool on a Pentium II processor, each lookup requires 3 additional clock cycles besides the ones needed for the memory accesses. Assuming a clock cycle of 3.33 nanoseconds and an L2 cache latency of 15 nanoseconds, search of MaeEast can be estimated in 55 nanoseconds or, equivalently, our method performs 18 millions of lookups per second.

Srinivasan and Varghese (1999) have proposed the use of multibit tries to represent routing tables used for Internet (IP) address lookups. They propose an O(n /sub */W/sup 2//sub */ k) dynamic programming algorithm to determine the strides for an optimal variable-stride trie that has at most k levels. Here, n is the number of prefixes in the routing table and W is the length of the longest prefix. We improve on this algorithm by providing an alternative dynamic programming formulation. The complexity of our algorithm is O(n/sub */W/sub */k), on real router data sets. This is an improvement by a factor of W over the corresponding algorithm of Srinivasan. Experiments conducted by us indicate that our variable-stride algorithm is between 2 and 17 times as fast for IPv4 routing table data.

Srinivasan and Varghese (1999) have proposed the use of multibit tries to represent routing tables used for Internet (IP) address lookups. They propose an O(k*W/sup 2/) time dynamic programming algorithm to determine the strides of an optimal k-level multibit fixed-stride trie when the longest prefix in the routing table has length W. The authors improve on this algorithm by providing an alternative dynamic programming formulation. While the asymptotic complexity of the resulting algorithm for fixed-stride tries is the same as that of the algorithm of Srinivasan and Varghese, experiments using real IPv4 routing table data indicate that their algorithm runs 2 to 4 times as fast.

Several parallel algorithms and parallel architectures have been developed for partitional clustering. Hierarchical clustering algorithms are also widely used in exploratory pattern analysis and unsupervised learning. The author proposes parallel algorithms on single-instruction/multiple-data (SIMD) machines for hierarchical clustering, which require intensive computation and large memory storage. The machine model includes a parallel memory system and an alignment network, to facilitate parallel access of both pattern matrix and proximity matrix. Since clustering algorithms tend to generate clusters even when applied to random data, clustering-tendency and cluster-validity studies are usually performed. The author proposes a parallel algorithm to compute one type of cluster validity measure global fit of hierarchy for quantitative data. For a problem with N patterns, considering validity study as well as clustering, the number of memory accesses is reduced from O(/sup 3/) on a sequential machine to O(N/sup 2/) on a SIMD machine with N processing elements (PEs). More general algorithms for different numbers of PEs are also given. >

The IP address lookup in the communication link technologies is becoming a major bottleneck by exploring the exact matching and the parallel hashing in each prefix length. In this paper, we present an algorithm for IP address lookup and collision resolution to reduce memory space and solve collision for high speed routing based on multiple table indexing structure. Our scheme makes possible direct access in a designated IP prefix without replicating the forwarding table entries, and provides efficient collision resolution for fast route lookup with only small memory. Simulation results indicate that our algorithm provides a faster lookup than the conventional lookup schemes.

IP address lookup algorithms can be evaluated on a number of metrics lookup time, update time, memory usage, and to a lesser extent, the time to construct the data structure used to support lookups and updates. Many of the existing methods are geared towards optimizing a specific metric, and hence do not scale well with the ever expanding routing tables and the forthcoming IPv6 with 128 bit long IP address. In contrast, our effort is directed at simultaneously optimizing multiple metrics and provide solutions that scale well to IPv6. In this paper, we present two IP address lookup schemes Elevator - Stairs algorithm and logW - Elevators algorithm. For a routing table with N prefixes, The Elevator - Stairs algorithm uses optimal O(N) memory, and achieves better lookup and update times than other methods with similar memory requirements. The logW - Elevators algorithm gives O(log W) lookup time, where W is the length of an IP address, while improving upon update time and memory usage. Experimental results using the MAE-West router with 29,487 prefixes show that the Elevator - Stairs algorithm gives an average throughput of 15.7 Million lookups per second (Mlps) using 459 KB of memory, and the logW - Elevators algorithm gives an average throughput of 21.41 Mlps with a memory usage of 1259 KB.

The increasing demand for portable electronics has caused power consumption to be a critical issue in the design process. Reducing the total power consumption in portable systems is important in order to maximize the run time with minimum requirements in size and weight of the batteries. Power consumption in memory-intensive operations can be reduced by minimizing the number of memory accesses. We describe two scheduling schemes under fixed hardware resource constraints which reduce the number of memory accesses by minimizing the number of intermediate variables that need to be stored. While the first scheme achieves this by post order traversal of the DFG, the second scheme achieves this by judiciously delaying the scheduling of some of the nodes. Experimental results show that these schemes require significantly fewer memory accesses compared to existing scheduling schemes.

The present era has witnessed spatial and temporal sharing of reconfigurable hardware or field programmable gate arrays (FPGAs) among multiple users. In such a scenario, the FPGA and related memory space is virtually partitioned and shared by many users. Criticality of tasks of different users is different and thus, their security strategies must vary. An adversary may pose as an user and cause rowhammer attacks, which is accessing its own memory rows in such a manner that will cause bit flips in nearby memory rows, accessed by a genuine user. Such attacks will go unnoticed as the adversary does not interfere with operations of others, but will cause erroneous result generation in task execution of genuine users. Existing works are silent on a mitigation policy for the present scenario. We explore how redundancy based approach may ensure security. However, this is associated with high area and power overhead, which indirectly increases cost. We propose a self aware approach that deploys self aware agents (SAA) to ensure criticality based reliability via a decentralized control mechanism in a multi FPGA platform. In the offline phase during testing, the number of memory access per unit time (MAPUT) that causes bit flips in nearby memory rows is noted and recorded in the SAAs. During runtime, the SAAs monitor the memory access made by user programs. On detecting MAPUT of user programs crossing the recorded MAPUT, it starts communicating with other SAAs and outsources the task for safe execution in another FPGA platform. To ensure prevention in future, it adopts certain policies like generating buffer memory rows or shuffling the memory locations of users or exchanging programs with other SAAs in advance. Nominal overhead of SAAs and large task success rate of high critical tasks during attacks from experimental results, depict prospects of our proposed mechanism.