A parallel processing architecture for FSS block-matching motion estimation

We present an architectural enhancement to reduce the power consumption of one dimensional full-search block-matching (FSBM) motion estimation. The architecture eliminates unnecessary computations and reduces the power consumption without sacrificing the optimality and high throughput. Both the new and old architectures are compared for power consumption in order to clarify the effectiveness.

In this paper, we present a scalable module-based architecture for block matching motion estimation algorithm of MPEG-4. The basic module comprises one set of processing elements based on one-dimensional systolic array architecture. To support various applications, modules of processing elements can be configured to form the processing element array to meet the requirements, such as variable block size, search range and computation power. And this proposed architecture has the advantage of few I/O port counts. Based on eliminating unnecessary signal transitions in the processing element, power dissipation of datapath can be reduced to about half without decreasing the picture quality.

Block matching motion estimation (BMME) plays a very important role in video coding. The performance of BMME greatly affects the quality of the encoded bit stream. In order to reduce the high computational demands of H.264 video encoder, a fast block matching motion estimation algorithm based on temporal and spatial motion correlation is proposed by the deep research of the characteristics of motion estimation. This algorithm well exploits the correlation between video sequence motion activity and macro-block coding pattern and motion vector statistic characteristics to employ different patterns. Experimental results show that the algorithm, without function losing of PNSR, can not only reduce the search complexity of motion estimation and the high computational demands but also raise the real-time performance of encoder.

High throughput, heavy bandwidth requirement, huge on-chip memory consumption, and complex data flow control are major challenges in high definition integer motion estimation hardware implementation. This paper proposes an efficient very large scale integration architecture for integer multi-resolution motion estimation based on optimized algorithm. There are three major contributions in this paper. First, this paper proposes a hardware friendly multi-resolution motion estimation algorithm well-suited for high definition video encoder. Second, parallel processing element (PE) array structure is proposed to implement three-level hierarchical motion estimation, only 256PEs are enough for one reference frame real-time high definition motion estimation by efficient PE reuse. Third, efficient on-chip reference pixel buffer sharing mechanism between integer and fractional motion estimation is proposed with almost 50% SRAM saving and memory bandwidth reduction. The proposed multi-resolution motion estimation algorithm reached a good balance between complexity and performance with rate distortion optimized variable block size motion estimation support. Also, we have achieved moderate logic circuit and on-chip SRAM consumption. The proposed architecture is well-suited for all MPEG-like video coding standards such as H.264, audio video coding standard, and VC-1.

This paper presents a highly parallel motion estimation architecture for High Efficiency Video Coding (HEVC) encoder. The proposed architecture has 16 processing units operating in parallel to calculate the sum of absolute difference values of all possible variable prediction block sizes. Hence, it calculates the bit cost regarding every partition in order to find the best matching candidate in terms of bit cost. The proposed unit processes block sizes from 4×4 up to 64×64. The proposed architecture was prototyped, simulated and synthesized using 65nm TSMC CMOS technology. At 720 MHz clock frequency, the proposed architecture processes 2K (1920×1080) resolution at 30 fps with ±27 (55×55) pixel search range using full search algorithm. Moreover, the proposed architecture is a flexible one and it can be used with different search algorithms to process higher resolutions such as 4K (3840×2160) resolution with 30 fps rate. To the best of our knowledge, the proposed architecture is one of the first ASIC motion estimation architectures in the literature for HEVC.

Chapter 4 - Basic Motion Estimation Techniques

This paper presents a new method for frame rate up‐conversion using sub‐sampled bilateral motion estimation, motion vector smoothing, simplified bidirectional motion compensated interpolation, and complex motion detection. The proposed method produces improved image quality and requires less computational complexity compared to conventional motion estimation. The average PSNRs of the proposed method for frame rate up‐conversion outperform those of the benchmark frame rate up‐conversion technique by up to 4.39 dB for the test sequences. Furthermore, the motion estimation of the proposed FRUC method reduces the required computational complexity to 12.5% of that required for full‐search block matching motion estimation.

Fractal compression is the lossy compression technique in the field of gray/color image and video compression. It gives high compression ratio, better image quality with fast decoding time but improvement in encoding time is a challenge. This review paper/article presents the analysis of most significant existing approaches in the field of fractal based gray/color images and video compression, different block matching motion estimation approaches for finding out the motion vectors in a frame based on inter-frame coding and intra-frame coding i.e. individual frame coding and automata theory based coding approaches to represent an image/sequence of images. Though different review papers exist related to fractal coding, this paper is different in many sense. One can develop the new shape pattern for motion estimation and modify the existing block matching motion estimation with automata coding to explore the fractal compression technique with specific focus on reducing the encoding time and achieving better image/video reconstruction quality. This paper is useful for the beginners in the domain of video compression.

The high computational cost of the motion estimation module in the new HEVC standard raises the need for efficient hardware architectures that can meet the real-time processing constraint. In addition, targeting HD and UHD resolutions increases the motion estimation processing cost beyond the capabilities of the currently existing architectures. This paper presents a highly parallel sum of absolute difference (SAD) architecture for motion estimation in HEVC encoder. The proposed architecture has 64 PUs operating in parallel to calculate the SAD values of the prediction blocks. It processes block sizes from 4×4 up to 64×64. The proposed architecture has been prototyped, simulated and synthesized on Xilinx Virtix-7 XC7VX550T FPGA. At 458 MHz clock frequency, the proposed architecture processes 30 2K resolution fps with ±20 pixels search range. The prototyped architecture utilizes 7% of the LUTs and 5% of the slice registers in Xilinx Virtex-7 XC7VX550T FPGA.

This paper presents two VLSI architectures for full search block matching motion estimation (ME) algorithm based on overlapped search data flow. The proposed VLSI architectures have three specific features: (1) they contain a processor element (PE) array which provides sufficient computational power and achieves 100% hardware efficiency; (2) they contain stream memory banks which provide scheduled data flow requested by PE for computing mean absolute distortion (MAD); and (3) they both have minimum memory bandwidth to save I/O pin-count.

Motion estimation is the most computationally intensive component of a video coding algorithm. It could consume as much as 75% of the total processing power of a video codec. Although various international video coding standards have adopted the block-matching approach for motion estimation, a designer can still have the freedom to choose a specific technique to find the motion vectors. Consequently, numerous techniques ranging from full search to simple fast search algorithms have been proposed and some of them have been implemented in VLSI chips. It should be emphasized that one of the most important requirements for an effective motion estimation algorithm is its ability to perform in real-time. The choice of a specific algorithm for implementation, however, depends very much on the intended application as well as the trade-offs between the desired performance and affordable complexity. In this paper, we first discuss what are the essential ingredients for an effective block-matching motion estimation, then briefly, describe what is the status of current technology, and finally, present some new activities in this vital area of research.

This paper proposes a parallel architecture for a successive elimination algorithm (SEA), which is used in block matching motion estimation. SEA effectively eliminates the search points within the search window and thus decreases the number of matching evaluation instances that require very intensive computations compared to the standard full search algorithm (FSA). The proposed architecture for SEA decreases the time to calculate the motion vector by 57 percent compared to FSA. The performance while applying the SEA to several standard video clips has been shown to be same compared to the standard FSA. The proposed architecture uses 16 processing elements accompanied with use of intelligent data arrangement and memory configuration. A technique for reducing external memory accesses has also been developed. The proposed architecture for SEA provides an efficient solution for applications requiring real-time motion estimations. For, it serves to compute motion vectors in less amount of time while requiring almost same power and some increase in area compared to a similar architecture for implementing the full search algorithm. A register-transfer level implementation as well as simulation results on benchmark video clips are presented. Relevant design statistics on area and power for comparing between SEA and FSA implementations are also provided.

Based on the concept of pseudo-phase and the sinusoidal orthogonal principles, we design a novel low-complexity and high throughput CORDIC (COordinate Rotation Digital Computer) architecture for half-pel motion estimation. The proposed multiplier-free and fully-pipelined parallel architecture works solely at DCT domain without interpolation of input images to meet the needs of high-quality high-bit rate video communications. In addition, the DCT-based nature enables us to efficiently combine the DCT and motion estimator into one single component of relatively low complexity. Its regular and modular structure along with only local interconnection provides a low-complexity solution for MPEG-2 and H.263 compatible video codec design on a dedicated single chip.

The H.264 video compression standard uses enhanced Motion Estimation (ME) features to improve both the compression ratio and the quality of compressed video. The two primary enhancements are the use of Variable Block Size Motion Estimation (VBSME) and multiple reference frames. These two additions greatly increase the computational complexity of the ME algorithm, to the point where a software based real-time (30 frames per second (fps)) implementation is not possible on present microprocessors. Thus hardware acceleration of the H.264 ME algorithm is necessary in order to achieve real-time performance for the implementation of the VBSME and multiple reference frames features. This thesis presents a scalable FPGA-based ME architecture that supports real-time H.264 ME for a wide range of video resolutions ─ from 640x480 VGA to 1920x1088 High Definition (HD). The architecture contains innovations in both the data-path design and memory organization to achieve scalability and real-time performance on FPGAs. At 37% FPGA device utilization, the architecture is able to achieve 31 fps performance for encoding full 1920x1088 progressive HDTV video.

Upcoming processor architectures support parallel processing on different levels. Multiple processing elements (PEs) run in parallel. The PEs consists of several functional units and the functional units allow sub-word parallelism (SWP), i.e. the parallel execution of operations with low data word width. In this paper, a parameterized mapping of algorithms onto massively parallel processor architectures (PAs) is derived which exploits both parallelism on PA and SWP on PE level. It establishes a correlation between the parameters of the algorithms and the parameters of the PA, which enables optimization strategies with respect to several expense factors of the PA. The design approach is based on the co-partitioning method and the partitioning of data dependencies. Both are used in a hierarchical manner. Besides the parameters of the PA (such as shape, number of PEs, number of sub-words processed in parallel, channels between the PEs, and their delay), the packing instructions for exploiting SWP can be deduced