A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems

Particle filters (PFs) are computationally intensive, which prevents them from being widely used in some real-time applications with high throughput requirements. A parallel implementation is a feasible approach to enable using PFs in these applications. However, effective resampling algorithms such as the Systematic Resampling (SR) algorithm are sequential in nature. In this paper, we propose a new form of the SR algorithm suitable for parallel implementation in an Application-Specific Instruction-set Processor (ASIP). Six custom instructions were designed for this reformulated SR algorithm. Experimental results show that the ASIP implementation of the reformulated SR algorithm, with four weights calculated in parallel, and eight categories defined by uniformly distributed numbers that are compared simultaneously to achieve a 30.6× speedup over the serial SR algorithm in a general-purpose processor. This comes at a cost of only 54K additional gates, or 68% overhead to be added to a base processor with 79K gates.

This paper is devoted to the resampling problem of particle filters. We firstly demonstrate the performance of classical Resampling algorithm (also called as systematic resampling algorithm) using a novel metaphor, through which the existing defects of Resampling algorithm is vividly reflected simultaneously. In order to avoid these defects, the exquisite resampling (ER) algorithm is induced which involves some exquisite actions such as comparing the weights by stages and generating the new particles based on quasi-Monte Carlo method. Simulations indicate that the proposed ER algorithm can reduce the sample impoverishment effectively and improve the accuracy of estimation evidently, which confirm that ER algorithm is a competitive alternative to Resampling algorithm.

The application specific instruction-set processor (ASIP) offers better computing performance and efficiency by exploiting a set of specific custom instructions (CI) in the processor. However, traditional approaches suffer from the problem that it costs so much computational resource to enumerate and select the optimal custom instructions. In this paper, instead of generating the custom instructions by enumerating all sub-graphs in the data flow graph, we propose a novel custom instruction generation algorithm based on analyzing the basic blocks (BB) which are the smallest execution units of the program. On the basis of characterizing the logic information and structure of basic blocks, both the identification and selection processes could be more efficient by focusing on the feasible candidates with better benefits. A Maximal Weight Independent Set-based formulation is set up to select the final custom instructions based on the efficient identification of candidate custom instructions with logic information of BBs. The experimental result shows that our algorithm can identify 55% more feasible CIs compared with the previous approach. With efficient identification process, we can finally get better CI designs with about 3.27X performance gain of the whole system.

In this paper, a flexible HW architecture for video-based driver assistance applications is presented. It comprises a customizable and extensible processor template and several task-specific HW accelerators. The proposed heterogeneous architecture allows utilization of the programmable processor core for control and low data rate tasks. For the acceleration of computationally intensive tasks of the application, special functional units and custom instructions can be added to the processor template to form an application specific instruction set processor (ASIP). Moreover, dedicated HW accelerators can be attached to the ASIP. To compare the diverse design options, a shape detection application for traffic sign detection is utilized as case study. It is shown that single tasks of a pure software implementation can be significantly accelerated by usage of special functional units by a factor of up to 35 and by usage of HW accelerators of up to 243. The proposed architecture has been mapped onto an FPGA and it could be shown that a realtime capable system can be realized.

Application-specific instruction-set processors (ASIPs) allow the designer to extend the instruction set of the base processor with selected custom instructions to tailor-fit the application. In this paper, with the help of a motivational example, we first demonstrate that different custom instructions are vulnerable to faults with varying probabilities. This shows that by ignoring the vulnerability to faults, traditional methods of instruction set customization can provide no guarantees on the reliability of the system. Apart from such inherent disparity in error vulnerability across custom instructions, each custom instruction can have multiple implementation choices corresponding to varying hardened levels. Hardening reduces the vulnerability to errors but this comes at the overhead of area costs and reduced performance gain. In this paper, we propose a framework to select custom instructions and their respective hardening levels such that reliability is optimized while the performance gain is satisfied and area costs are met as well. Our framework is based on a novel analytical method to compute the overall system reliability based on the probability of failure of individual instructions. Wide range of experiments that were conducted illustrate how our tool navigates the design space to reveal interesting tradeoffs.

This article discusses a MATLAB-to-C vectorizing compiler that exploits custom instructions, for example, for Single Instruction Multiple Data (SIMD) processing and instructions for complex arithmetic present in Application-Specific Instruction Set Processors (ASIPs). Custom instructions are represented via specialized intrinsic functions in the generated code, and the generated code can be used as input to any C/C++ compiler supporting the target processor. Furthermore, the specialized instruction set of the target processor is described in a parameterized way using a target processor-independent architecture description approach, thus allowing the support of any processor. The compiler has been used for the generation of application code for two different ASIPs for several benchmarks. The code generated by the compiler achieves a speedup between 2× --74× and 2× --97× compared to the code generated by the MathWorks MATLAB-to-C compiler. Experimental results also prove that the compiler efficiently exploits SIMD custom instructions achieving a 3.3 factor speedup compared to cases where no SIMD processing is used. Thus the compiler can be employed to reduce the development time/effort/cost and time to market through raising the abstraction of application design in an embedded systems/system-on-chip development context.

In modern SoC designs, more and more application specific instruction-set processors (ASIPs) are used. They enable a trade off between the flexibility due to the software implementation of algorithms and hardware efficiency arising from the ASIP architecture which is optimized with respect to the application. In this paper, it is shown that the total power dissipation could be reduced by distributing the software tasks on several identical ASIP instances although the throughput of a single ASIP would be sufficient for all tasks. In addition, it is shown that for power comparisons of processor instances, the number of executed lines of code is a parameter which gives more insight into power comparisons than the clock rate.

A local weight mean comparison scheme for high-speed particle filters along with its corresponding architecture is presented. The proposed scheme arranges a particle index by a comparison between the relevant weight and the current mean weight so that as many high-weighted particles as possible can be firstly accessed in the next sampling step. It breaks the sequential nature of resampling and basically maintains the same accuracy as that of the systematic resampling (SR) scheme. The proposed architecture pipelines the current resampling step and the next sampling step, and improves the speed by times compared with generic architectures based on the SR scheme and the residual systematic resampling scheme.

We describe a new approach for creating hardware description language (HDL) specifications for custom instructions, to form part of the instruction-set architecture (ISA) of an application specific instruction set processor (ASIP). Our approach integrates fully into the traditional C development process, binding tightly with software source code and simplifying the ASIP optimisation process. Our tool is also free software, facilitating its use in future research.KeywordsClock CycleIntegrate Development EnvironmentBenchmark ProgramManual ImplementationCustom UnitThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper presents a real-time FPGA implementation of the posterior system state estimation in dynamic models, which is developed using particle filter algorithm. Specially, our system is constructed by parallel resampling (FO-resampling) algorithm on a stream-based architecture. To be precise, the resampling is accomplished in a valid pixel area of an input image frame while prediction and update of particles are performed in a synchronization region, thus our approach achieves realtime performance of 60 fps for VGA images, synchronized with the camera pixel throughput without using any external memory devices. Through evaluation with an object tracking benchmark video, the tradeoff relationship between tracking quality and the number of particles is analyzed to find an appropriate hardware parameters. In addition, we address improvement of resource utilization for our particle filter architecture, especially by using a higher clock frequency to reuse hardware resources in a time sharing manner. The implementation experiments reveal that the proposed approach allows the original design to be fitted in a smaller FPGA chip. However, we also demonstrate this size reduction approach has an overhead of 2.7 to 3.0 times power consumption compared to original designs with a slow clock frequency.

The problem of tracking targets precisely is important both in military and civilian applications. There are different approaches to tracking targets precisely. Particle filters have been used frequently for this purpose in recent years. Different resampling algorithms have been proposed for particle filters. In this study, the performance of the minimum sampling variance resampling algorithm is evaluated. With this algorithm, the performance of different resampling algorithms on different particle numbers, different measurement and process noise, and on different motion models are compared

Customized instructions (CIs) implemented using custom functional units (CFUs) have been proposed as a way of improving performance and energy efficiency of software while minimizing cost of designing and verifying accelerators from scratch. However, previous work allows CIs to only communicate with the processor through registers or with limited memory operations. In this work we propose an architecture that allows CIs to seamlessly execute memory operations without any special synchronization operations to guarantee program order of instructions. Our results show that our architecture can provide 24\% energy savings with 14% performance improvement for 2-issue and 4-issue superscalar processor cores.

PurposeThe purpose of this paper is to focus on applications related to the hyperthermia treatment of cancer, with heating imposed either by a laser in the near-infrared range or by radiofrequency waves. The particle filter algorithms are compared in terms of computational time and solution accuracy.Design/methodology/approachThe authors extend the analyses performed in their previous works to compare three different algorithms of the particle filter, as applied to the hyperthermia treatment of cancer. The particle filters examined here are the sampling importance resampling (SIR) algorithm, the auxiliary sampling importance resampling (ASIR) algorithm and Liu & West’s algorithm.FindingsLiu & West’s algorithm resulted in the largest computational times. On the other hand, this filter was shown to be capable of dealing with very large uncertainties. In fact, besides the uncertainties in the model parameters, Gaussian noises, similar to those used for the SIR and ASIR filters, were added to the evolution models for the application of Liu & West’s filter. For the three filters, the estimated temperatures were in excellent agreement with the exact ones.Practical implicationsThis work may help medical doctors in the future to prescribe treatment protocols and also opens the possibility of devising control strategies for the hyperthermia treatment of cancer.Originality/valueThe natural solution to couple the uncertain results from numerical simulations with the measurements that contain uncertainties, aiming at the better prediction of the temperature field of the tissues inside the body, is to formulate the problem in terms of state estimation, as performed in this work.

Several techniques have been proposed to reduce the energy consumption of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with minimal change in the instruction set (IS), they often fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this chapter we present an energy-efficient IS synthesis that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction fetch count. Experimental results with a typical embedded RISC processor show that the proposed energy-efficient IS synthesis technique can generate application-specific ISs that are up to 40% more energy-efficient over the native IS for several application benchmarks.

Nowadays, vehicle tracking is a vital approach to assist and improve the road traffic control, surveillance and security systems by having the detail of the captured vehicle information. In past, many tracking techniques have been implemented and suffered from the well known 'occlusion' problems. Increasing the accuracy of the tracking algorithm has caused the computational cost due to the inflexibility to adapt the partial and fully occluded situations. Besides occlusion, appearance of new objects and background noises in the captured videos increase the difficulties of continuously tracking the labelled vehicles. In this paper, an adaptive particle filter approach has been proposed as the tracking algorithm to solve the vehicle occlusion problem. In order to solve the common particle filter degeneracy problem, the proposed particle filter is equipped with the adaptive resampling algorithm which is capable of dealing with various occlusion incidents. The experimental results show that enhancement of the particle filter via resampling algorithm has been robustly tracking the vehicles, and significantly improve the accuracy in tracking the occluded vehicles without compromising the processing time.