A post-processing method for true random number generators based on hyperchaos with applications in audio-based generators

True random number generators (TRNG) are widely used to generate encryption keys in information security systems [1]–[2]. In TRNG, entropy source is a critical module who provides the source of randomness of output bit stream. The unavoidable electrical noise in circuit becomes an ideal entropy source due to its unpredictability. Among the methods of capturing electrical noise, ring oscillator-based entropy source makes the TRNG most robust to deterministic noise and 1/f noise which means the strongest anti-interference capability, so it is simple in structure and easy to integrate [3]. Thus, great research attention has focused on ring oscillator-based TRNGs [3] –[7]. In [4], a high-speed TRNG with 100Mbps output bit rate was proposed, but it took up too much power and area. A TRNG based on tetrahedral ring oscillator was proposed in [5]. Its power consumption was very low but the output bit rate was also very low. A ring oscillator-based TRNG with low output bit rate but high power was proposed in [7]. In a word, none of the above architectures achieve an appropriate compromise between bit rate and power consumption. This work presents a new feedback architecture of TRNG based on tetrahedral ring oscillator. The output random bit stream generates a relative random control voltage that acts on the transmission gates in oscillator through a feedback loop, thus increasing phase jitter of the oscillator and improving output bit rate. Furthermore, an XOR chain-based post-processing unit is added to eliminate the statistical deviations and correlations between raw bits.

A true random number generator (TRNG) is essential to ensure information security for Internet of Things (IoT) edge devices. While pseudorandom number generators (PRNGs) have been instrumental, their deterministic nature limits their application in security-sensitive scenarios. In contrast, hardware-based TRNGs derived from physically unpredictable processes offer greater reliability. This study demonstrates a peripheral-free TRNG utilizing two cascaded three-stage inverters (TSIs) in conjunction with an XOR gate composed of monolayer molybdenum disulfide (MoS2) field-effect transistors (FETs) by exploiting the stochastic charge trapping and detrapping phenomena at and/or near the MoS2/dielectric interface. The entropy source passes the NIST SP800-90B tests with a minimum normalized entropy of 0.8780, while the generated bits pass the NIST SP800-22 randomness tests without any postprocessing. Moreover, the keys generated using these random bits are uncorrelated with near-ideal entropy, bit uniformity, and Hamming distances, exhibiting resilience against machine learning (ML) attacks, temperature variations, and supply bias fluctuations with a frugal energy expenditure of 30 pJ/bit. This approach offers an advantageous alternative to conventional silicon, memristive, and nanomaterial-based TRNGs as it obviates the need for extensive peripherals while harnessing the potential of atomically thin 2D materials in developing low-power TRNGs.

A true random number generator (TRNG) is suitable for generating secure keys and nonces. TRNGs implemented in IoT devices must be small in scale and have low power consumption. The random number sequence generated by TRNG needs to have high entropy immediately after startup and a stable state. In this paper, three types of ring oscillator type TRNGs, TERO-based, COSO-based, and STR-based TRNG, are implemented on Zynq-7010. When these TRNGs are implemented as a single entropy source, it is challenging to implement them because it is necessary to evaluate the layout and wiring for each FPGA. This paper proposes a TRNG configuration, which exclusively ORs the outputs of multiple entropy sources. We show that this configuration can reduce the implementing difficulty and realize high entropy. For the random number sequence evaluation, we use the statistical test of NIST SP800-90B and BSI AIS 20/31. In addition, the random number sequence immediately after the startup is also statistically evaluated. As a result, our proposed TRNGs generate high entropy random numbers and are easy to implement on FPGA when we implement TRNGs with eight single entropy sources for TERO-based TRNG, 48 for COSO-based TRNG, and two for STR-based TRNG, respectively.

Random numbers play a key-role in cryptography, since they are used, e.g., to define enciphering keys or passwords [1]. Nowadays, the generation of random numbers is obtained referring to two types of devices, that are often properly combined together: True Random Number Generators (TRNGs), and Pseudo Random Number Generators (PRNGs). The former are devices that exploit truly stochastic physical phenomena [2, 3, 4, 5, 6], such as the electronic noise or the chaotic dynamics of certain nonlinear systems: for these devices the output sequences have an intrinsic degree of unpredictability, that is measured referring to the theoretical tools provided by Information Theory (e.g., in terms of the Shannon entropy) [7,4]. On the other hand, PRNGs are deterministic periodic finite state machines whose aim is to emulate, within the period, the random behavior of a truly random source of numbers. From a theoretical point of view, due to their deterministic nature, PRNGs are potentially predictable by observing their generated sequences [8, 9, 10, 1]. Nevertheless, in literature some families of PRNGs are classified to be ‘secure’, meaning that their algorithmic structure involves calculations that in average, referring to the prediction task, require an amount of computation time that is asymptotically unfeasible with the size of the problem, when referring to both the computational equipment at disposal and the known computing fastest algorithms [1,11]. It is worth noting that a given generator, even if belonging to an asymptotically secure family of PRNGs, can generate short periodic (and unsecure) sequences for several values of the initial seed. Therefore, apart from the cryptographic robustness of their algorithmic structure, a cryptographic PRNG must generate sequences that are acceptable from a statistical point of view, i.e., that pass a certain number of standard statistical tests [1, 12].

Quantum random number generator (QRNG) allows obtaining true random bit sequences. In QRNG based on quantum nature of vacuum, optical beam splitter with two inputs and two outputs is normally used. We compare mathematical descriptions of spatial beam splitter and fiber Y-splitter in the quantum model for QRNG, based on homodyne detection. These descriptions were identical, that allows to use fiber Y-splitters in practical QRNG schemes, simplifying the setup. Also we receive relations between the input radiation and the resulting differential current in homodyne detector. We experimentally demonstrate possibility of true random bits generation by using QRNG based on homodyne detection with Y-splitter.

The vital characteristic of randomness is unpredictability. Thus any regularity will compromise the application of random numbers. Quantum random number generators (QRNGs) can provide intrinsic unpredictable randomness based on the nature of quantum physics, while pseudo-random number generator can not due to the origination of deterministic algorithms or physical processes. However, commonly used traditional test suits are rigorously to test the statistical properties, and the unpredictability of random numbers is still difficult to test. To verify which sources of random numbers are truly unpredictable, in this paper, we propose a new randomness testing method with the artificial neural network (ANN). Random number sequences generated by four different kinds of sources are tested, which are the natural number λ, the linear congruence generator (LCG) pseudo-random algorithm, the Mersenne Twister (MT) pseudorandom algorithm and the QRNG based on vacuum noise, respectively. The testing results indicate that the random sequences from natural number λ and LCG fail to pass our randomness test, while the other two kinds of sequences pass the test successfully due to the relatively simple structure of our ANN. As the complexity of the ANN and the amount of computing power involved increasing, this test method has potential to predict the MT random numbers, and it is also expected that the quantum random numbers can not pass the test with unpredictability no matter how complex the ANN is.

By measuring the amplified spontaneous emission (ASE) noise of the superluminescent light emitting diodes, we propose and realize a quantum random number generator (QRNG) featured with practicability. In the QRNG, after the detection and amplification of the ASE noise, the data acquisition and randomness extraction which is integrated in a field programmable gate array (FPGA) are both implemented in real-time, and the final random bit sequences are delivered to a host computer with a real-time generation rate of 1.2 Gbps. Further, to achieve compactness, all the components of the QRNG are integrated on three independent printed circuit boards with a compact design, and the QRNG is packed in a small enclosure sized 140 mm × 120 mm × 25 mm. The final random bit sequences can pass all the NIST-STS and DIEHARD tests.

This paper presents a novel approach to enhancing the security and reliability of drone communications through the integration of Quantum Random Number Generators (QRNG) in Frequency Hopping Spread Spectrum (FHSS) systems. We propose a multi-drone framework that leverages QRNG technology to generate truly random frequency hopping sequences, significantly improving resistance against jamming and interception attempts. Our method introduces a concurrent access protocol for multiple drones to share a QRNG device efficiently, incorporating robust error handling and a shared memory system for random number distribution. The implementation includes secure communication protocols, ensuring data integrity and confidentiality through encryption and Hash-based Message Authentication Code (HMAC) verification. We demonstrate the system’s effectiveness through comprehensive simulations and statistical analyses, including spectral density, frequency distribution, and autocorrelation studies of the generated frequency sequences. The results show a significant enhancement in the unpredictability and uniformity of frequency distributions compared to traditional pseudo-random number generator-based approaches. Specifically, the frequency distributions of the drones exhibited a relatively uniform spread across the available spectrum, with minimal discernible patterns in the frequency sequences, indicating high unpredictability. Autocorrelation analyses revealed a sharp peak at zero lag and linear decrease to zero values for other lags, confirming a general absence of periodicity or predictability in the sequences, which enhances resistance to predictive attacks. Spectral analysis confirmed a relatively flat power spectral density across frequencies, characteristic of truly random sequences, thereby minimizing vulnerabilities to spectral-based jamming. Statistical tests, including Chi-squared and Kolmogorov-Smirnov, further confirm the unpredictability of the frequency sequences generated by QRNG, supporting enhanced security measures against predictive attacks. While some short-term correlations were observed, suggesting areas for improvement in QRNG technology, the overall findings confirm the potential of QRNG-based FHSS systems in significantly improving the security and reliability of drone communications. This work contributes to the growing field of quantum-enhanced wireless communications, offering substantial advancements in security and reliability for drone operations. The proposed system has potential applications in military, emergency response, and secure commercial drone operations, where enhanced communication security is paramount.

Currently, True Random Number Generation (TRNG) is relatively slow, utilizing natural, physical processes as its entropy source. Other types of random numbers, such as Pseudo-Random Numbers, lack true randomness as eventually they repeat, but can be generated with great speed. The main idea of the work presented in this paper is to introduce parallel random number generation as a scalable means of increasing the rate of true random number generation in hardware to match and surpass that of Pseudo-Random Number Generators (PRNGs). Using a Raspberry Pi platform, this work will combine two (2) standard TRNGs to form one (1) unified, Parallel - True Random Number Generator (P-TRNG), with more than twice the output performance rate of its component TRNGs, and with demonstrated scalability.

Random number generation is a fundamental aspect of computer science, cryptography, simulations, and statistical sampling. This paper explores the definitions, classifications, and implementations of random and pseudo-random number generators (RNGs and PRNGs). We examine true random number generators (TRNGs), which derive randomness from physical phenomena, and pseudo-random number generators (PRNGs), which use deterministic algorithms to produce sequences that mimic randomness. Case studies, including Random.org, HotBits, laser-based RNGs, and the Linux random number generator, illustrate practical implementations. We also discuss vulnerabilities, security considerations, and the importance of entropy in generating unpredictable sequences.

Phase-locked loop (PLL) based true random number generator (TRNG) is very well suited for security applications using field programmable gate arrays (FPGAs) because most of FPGAs feature hardwired PLL blocks. PLL based TRNGs (PLL-TRNGs) are easy to implement and do not require manual placement or routing. The design of such TRNGs is also highly portable within the same device family. This is not the case in many other TRNG designs. However, the design of a PLL-TRNGs is not a trivial task. Due to many PLL parameters, which need to be fine tuned to achieve required security and speed requirements, an exhaustive design space exploration is practically not feasible. Thus, the designers are required to go through many trial and error cycles of manual parameter tweaking and the results are still not guaranteed to be optimal. In this paper, we use a genetic algorithm (GA) based optimization to generate a suitable configuration of the PLL-TRNG, such that it is secure and reaches high output bit rate. GA optimization allows to take into account physical limits of the PLL, such as input/output frequency, and maximum voltage controlled oscillator (VCO) frequency, which avoids invalid configurations and reduces the development time. The method has proven to be very efficient and it significantly reduces the design time without compromising the security. All the presented configurations were tested on recent FPGA families and the statistical quality of the resulting TRNG configurations was verified using the AIS 31 test suite.

The explosive growth of Internet of Things (IoT) devices has demanded the urgency of robust data security to protect private information. The random numbers generated by pseudo‐random number generators (PRNGs) play a crucial role in cryptographic algorithms. However, these sequences have become increasingly predictable due to advances in computing power and machine learning. Therefore, the development of true random number generators (TRNGs), which exploit the intrinsic hardware‐level randomness as an entropy source, is important for future data security. In this study, we present TRNG circuits that harness the inherent stochasticity of a multilayer hBN volatile memristor. The fabricated device exhibits highly stable threshold switching with low set/hold voltages and a significantly high on/off ratio. We implement a spike generator by integrating the threshold switching memristor with passive components. Digitization with a fixed‐reference comparator directly converts output spikes into bitstreams that successfully pass NIST randomness tests without postprocessing. The practical utility of the TRNG is demonstrated through XOR‐based encryption and decryption of black‐and‐white and grayscale images, resulting in noise‐like encrypted data and perfect recovery of the originals using identical keys. These results establish 2D hBN‐based threshold switching memristors as compelling hardware entropy sources for secure, next‐generation electronic systems.

We describe a methodology and standard of proof for experimental claims of quantum random-number generation (QRNG), analogous to well-established methods from precision measurement. For appropriately constructed physical implementations, lower bounds on the quantum contribution to the average min-entropy can be derived from measurements on the QRNG output. Given these bounds, randomness extractors allow generation of nearly perfect ``$\ensuremath{\epsilon}$-random'' bit streams. An analysis of experimental uncertainties then gives experimentally derived confidence levels on the $\ensuremath{\epsilon}$ randomness of these sequences. We demonstrate the methodology by application to phase-diffusion QRNG, driven by spontaneous emission as a trusted randomness source. All other factors, including classical phase noise, amplitude fluctuations, digitization errors, and correlations due to finite detection bandwidth, are treated with paranoid caution, i.e., assuming the worst possible behaviors consistent with observations. A data-constrained numerical optimization of the distribution of untrusted parameters is used to lower bound the average min-entropy. Under this paranoid analysis, the QRNG remains efficient, generating at least 2.3 quantum random bits per symbol with 8-bit digitization and at least 0.83 quantum random bits per symbol with binary digitization at a confidence level of 0.999 93. The result demonstrates ultrafast QRNG with strong experimental guarantees.

True random number generators (TRNGs) are essential components for a wide range of chips. This paper presents a novel method to design true random number generators on FPGA. By using cross-coupled NAND gates and manual routing, the proposed TRNG is implemented on Xilinx Virtex XC5VLX50T FPGA with a self-calibration and post processing circuit. The proposed TRNG can achieve the random bit rate from 600Kbps to 30Mbps, while consuming 4 LUTs to 220 LUTs. The TNRG passed all NIST tests with high entropy. Compared with other design, the proposed TRNG can achieve high quality of randomness and high throughput rate. Thus, the proposed circuit can be used in true random number generator design on FPGA.

This brief proposes a true-random number generator (TRNG) based on a successive approximation register (SAR) analog-to-digital converter (ADC). After the SAR ADC has finished conversion, the comparator is fired again to quantize the residue. The 1-bit quantized residue acts as a true random sequence and no additional circuits are required for the TRNG. A prototype fabricated in 65nm process acts as a TRNG over 0.6V-1.2V power supply and -5°C to 50°C temperature range without any calibration or post-processing. The TRNG outputs a random sequence at 1.25Mbps and consumes state-of-the-art energy of 0.22pJ/bit.