A Practical Approach to Verification of Mobile Systems Using Net Unfoldings

The unfolding technique is an efficient tool to explore the runs of a Petri net in a true concurrency semantics, i.e. without constructing all the interleavings of concurrent actions. But even small real systems are never modeled directly as ordinary Petri nets: they use many high-level features that were designed as extensions of Petri nets. We focus here on two such features: colors and compositionality. We show that the symbolic unfolding of a product of colored Petri nets can be expressed as the product of the symbolic unfoldings of these nets. This is a necessary result in view of distributed computations based on symbolic unfoldings, as they have been developed already for standard unfoldings, to design modular verification techniques, or modular diagnosis procedures, for example. The factorization property of symbolic unfoldings is valid for several classes of colored or high-level nets. We derive it here for a class of (high-level) open nets, for which the composition is performed by connecting places rather than transitions.

In this paper, we deal with the problem of critical observability for discrete event systems modeled by labeled safe Petri nets (PNs). Critical observability is a property originated from the safety-critical applications of cyber-physical systems. For the purpose to check this property of a PN model, it is necessary to detect whether the current state of the net system is, or is not in a set of critical states representing dangerous operations. The main results of the work is to propose a necessary and sufficient condition for checking the critical observability in safe PNs when the set of critical states is modeled by an arbitrary set of reachable markings. The proposed method exploits the solution of integer linear programming problems. Finally, several examples are discussed to demonstrate the efficiency of the proposed approach.

A method to find the minimized state machine cover of live and safe Petri nets (PNs) is proposed in this paper. It is required that a cover be obtained in some implementation methods of PN-based control algorithms and other applications such as data mining. Most of the known methods of its computation have at least exponential time and space complexity; this is true not only for the methods which guarantee a minimal cover is obtained but also for some methods of finding approximate solutions. The proposed algorithm is an approximation algorithm and has polynomial computational complexity. The experimental verification shows a very high efficiency of the presented technique. The proposed method is especially valuable in the case of large systems where a solution is obtained hundreds of times quicker than by other methods.

Model checking of systems with many identical timed processes

Petri nets generating all the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> binary n-vectors as their marking vectors are not only of theoretical interest but also are of practical importance. In this note, we demonstrate the existence of a disconnected 1-safe Petri net whose reachability tree is homomorphic to the n-dimensional complete lattice L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> . This makes the problem of characterizing the 1-safe Petri nets that generate all the binary n-vectors as marking vectors exactly once appear more intricate.

Non-interference characterises the absence of undesired information flows in a computing system, by asking that actions with higher level of confidentiality do not cause any observable effect at the lower levels. In many concrete applications, this requirement is too strict and the abstract model is enriched with some form of downgrading, namely with the possibility of declassifying information, thus allowing for a controlled form of leakage. This paper focuses on BINI (Bisimilarity-based Intransitive non-interference), a formalisation of non-interference with downgrading in the setting of Petri nets. Generalising some previous works, we provide a causal characterisation of BINI in terms of the unfolding semantics, a true concurrent semantics of Petri nets. Building on this, we design an algorithm for checking BINI on safe Petri nets which relies on the construction of suitable complete prefixes of the unfolding. The algorithm is implemented in a prototype tool and some preliminary tests are quite encouraging as they suggest that the management of downgrading does not cause any significant performance decay.

A definition of “action refinement” is given for an operational model of concurrent processes based on safe Petri Nets, generalizing previous work of Vogler and van Glabbeek/Goltz. A failure-style denotational semantics is described for process nets. The semantics is fully abstract for Hennessy Testing-equivalence on nets acting as refinement operators as well as operands. The semantics embodies the notions of deadlock, failures and divergences found in the Hoare/CSP and Hennessy Testing-equivalence theories, as well as some of the basic ideas of “pomset runs” and “causal” partial orders of Net theory.

A set of necessary conditions for a Petri net to be plain, pure and safe is given. Some applications of these conditions both in practice (for Petri net synthesis), and in theory (e.g., as part of a characterisation of the reachability graphs of live and safe marked graphs) are described.

The approach aims at solving the above problems by including the analysis and verification of two different levels of software development process–design level and implementation level-and bridging the gap between software architecture analysis and verification and the software product. In the architecture design level, to make sure the design correctness and attack the large scale of complex systems, the compositional verification is used by dividing and verifying each component individually and synthesizing them based on the driving theory. Then for those properties that cannot be verified on the design level, the design model is translated to implementation and runtime verification technique is adapted to the program. This approach can highly reduce the work on the design verification and avoid the state-explosion problem using model checking. Moreover, this approach can ensure both design and implementation correctness, and can further provide a high confident final software product. This approach is based on Software Architecture Model (SAM) that was proposed by Florida International University in 1999. SAM is a formal specification and built on the pair of component-connector with two formalisms – Petri nets and temporal logic. The ACV approach places strong demands on an organization to articulate those quality attributes of primary importance. It also requires a selection of benchmark combination points with which to verify integrated properties. The purpose of the ACV is not to commend particular architectures, but to provide a method for verification and analysis of large scale software systems in architecture level. The future research works fall in two directions. In the compositional verification of SAM model, it is possible that there is circular waiting of certain data among different component and connectors. This problem was not discussed in the current work. The translation of SAM to implementation is based on the restricted Petri nets due to the undecidable issue of high level Petri nets. In the runtime analysis of implementation, extraction of the execution trace of the program is still needed to get a white box view, and further analysis of execution can provide more information of the product correctness.

This chapter introduces a theoretical frame for the Process Definition (PD) validation in Workflow or in those processes with temporal restrictions. The Interface 1 of Workflow makes the PD of the Work Flow Reference Model. This interface combined with Petri Nets with Clocks (PNwC) allows the formalization and verification of systems, based on the Petri Net theory and the extension. This extension allows the specification of temporal requirements via clocks specification, using temporal invariants for the places and temporal conditions in the transitions.

In this chapter, we present applications of regions and elementary (or quasielementary) net synthesis for the design of speed independent circuits. Asynchronous circuit design is a wide and complex field that encompasses other topics than Petri nets. We refer the reader to the book [46] for a complete presentation of this field. We will limit ourselves to assessing the roles played by regions and net synthesis for solving the Complete State Coding problem (CSC). This crucial problem motivated the implementation of a net synthesis procedure in Petrify, a general design tool for asynchronous circuits presented in [46]. It must be acknowledged that different methods based on net unfoldings and SAT solvers are now preferred over net synthesis for solving the CSC problem.

Over the last few years there has been an increasing research effort directed towards the automatic verification of infinite-state systems. There are now verification techniques for many classes of infinite-state systems, including timed and hybrid automata, petri nets, pushdown systems, systems with FIFO channels, systems with a simple treatment of data, etc. In this tutorial, we will cover general verification techniques that have been used for infinite-state and parameterized systems, and try to show their power and limitations. Such techniques are e.g., symbolic model-checking techniques, abstraction, induction over the networks structure, widening, and automata-based techniques. We will focus on linear-time safety and liveness properties.

Petri nets have been extensively applied for specification, design, verification, performance evaluation, and simulation of discrete-event control systems. A real-time Petri net is a further improvement over the timed Petri net. The paper proposes to use a real-time Petri net to represent the stage programming of a programmable logic controller for a discrete-event control system. An illustrated example is used to explore the Petri net-based PLC stage programming methodology.

Modelling and Verification of PLC-Based Systems Programmed with Ladder Diagrams

Modeling of interval P-time Petri nets using dioid algebra