A predictive distributed congestion metric and its application to technology mapping

A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, especially for mapping with tight and complicated constraints. In this paper, we propose a procedure which takes into account a large number of circuit structures during technology mapping. A set of circuit structures is compactly encoded in a single graph, and the procedure dynamically modifies the set during technology mapping by applying simple local transformations to the graph. State-of-the-art technology mapping algorithms are naturally extended, so that the procedure finds an optimal tree implementation over all of the circuit structures examined. We show that the procedure effectively explores the entire solution space obtained by applying algebraic decomposition exhaustively. However, the run time is proportional to the size of the graph, which is typically logarithmic in the number of circuit structures encoded. The procedure has been implemented and used for commercial design projects, We present experimental results on benchmark examples to demonstrate its effectiveness.

In this paper, we propose a new FPGA design algorithm, Maple-opt, in which technology mapping, placement, and global routing are executed so that the delay of each critical signal path in an input circuit is within a specified upper bound imposed on it. The basic algorithm of Maple-opt is top-down hierarchical bi-partitioning of regions. Technology mapping onto logic-blocks of FPGAs, their placement, and global routing are determined simultaneously in each hierarchical process. This simultaneity leads to less congested layout for routing. In addition to that, Maple-opt computes a lower bound of delay for each path with a constraint value and determines critical paths based on the difference between the lower bound and the constraint value dynamically in each hierarchical process. Two delay reduction processes are executed for the critical paths; one is routing delay reduction and the other is logic-block delay reduction. Routing delay reduction is realized such that, when bi-partitioning a region, each constrained path is assigned to one subregion. Logic-block delay reduction is realized such that each constrained path is mapped onto fewer logic-blocks. Experimental results for some benchmark circuits show its efficiency and effectiveness.

A new field programmable gate array (FPGA) design algorithm, Maple-opt, is proposed for technology mapping, placement, and global routing subject to a given upper bound of critical signal path delay. The basic procedure of Maple-opt is viewed as top-down hierarchical bipartition of a layout region. In each bipartitioning step, technology mapping onto logic blocks of FPGAs, their placement, and global routing are determined simultaneously, which leads to a more congestion-balanced layout for routing. In addition, Maple-opt is capable of estimating a lower bound of the delay for a constrained path and of extracting critical paths based on the difference between the lower bounds and given constraint values in each bipartitioning step. Two delay-reduction procedures for the critical paths are applied; routing delay reduction and logic-block delay reduction. The routing delay reduction is done by assigning each constrained path to a single subregion when bipartitioning a region. The logic-block delay reduction is done by mapping each constrained path onto a smaller number of logic blocks. Experimental results for benchmark circuits demonstrate that Maple-opt reduces the maximum number of tracks per channel by a maximum of 38% compared with existing algorithms while satisfying almost all the path delay constraints.

Technology mapping and placement have a significant impact on delays in standard cell-based very large scale integrated circuits. Traditionally, these steps are applied separately to optimize the delays, possibly since efficient algorithms that allow the simultaneous exploration of the mapping and placement solution spaces are unknown. In this paper, we present an exact polynomial time algorithm for delay-optimal placement of a tree and extend the same to simultaneous technology mapping and placement for the optimal delay in the tree. We extend the algorithm by employing Lagrangian relaxation technique, which assesses the timing criticality of paths beyond a tree, to optimize the delays in directed acyclic graphs. Experimental results on benchmark circuits in a 70 nm technology show that our algorithms improve timing significantly with remarkably less runtimes compared to a competitive approach of iterative conventional timing-driven mapping and multilevel placement.

Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a polynomial time algorithm which can run in O(n3) time to generate an efficient solution where n is the total number of gates in the circuit. The proposed algorithm partitions the graph representing the given circuit into subgraphs such that the solution can be obtained by merging the subgraph solutions. The greedy technique is then used to find the solution for each subgraph. It is shown that except for some cases the greedy method can find an optimal solution of a given problem. We have tested our algorithm on a set of benchmark examples. The experimental results demonstrate the effectiveness of our algorithm.

Recent generation of FPGA devices takes advantage of speed and density benefits resulted from heterogeneous FPGA architecture, in which several basic LUTs can be combined to form one larger size LUT called Macro. Large Macros not only decrease network depth efficiently but also reduce area. In this paper, a new technology mapping algorithm, named MacroMap is proposed for the heterogeneous FPGAs with effective area estimation to overcome the main disadvantage that traditional technology mapping algorithms only generate one kind of typical K-LUT and cannot make full use of LUTs with different sizes (basic LUTs and Macros). Experimental results show that MacroMap can obtain 19% gain on area while keeping the network depth optimal compared with the existing heterogeneous FPGA mapping algorithm heteromap <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[8]</sup> .

This paper presents a CAD technology mapping algorithm, called Wmap, for k-LUT based FPGAs. Wmap is designed to optimize both routability and performance, giving priority to routability. Since interconnection in a FPGA must be accomplished with limited routing resources, routability is the most important objective in a technology mapping algorithm. Thus, the primary goal of Wmap is the production of a design with a minimum total wire number. After a routable design has been generated, performance is then optimized from the remaining degrees of freedom. The min-cut algorithm is first used to partition a graph representing a Boolean network into clusters so that every cluster can be implemented by a CLB in the FPGA and so that the total number of interconnection wires is minimum. Without increasing the number of wires needed, the clusters are then merged into larger clusters by using an existing labeling algorithm that optimizes the performance of the generated network. Finally, CLBs are further merged to minimize the total number of CLBs. This algorithm has been tested on the MCNC benchmark circuits. Compared with the result of a widely used algorithm that considers performance only, Wmap produces a result that uses about 20% less interconnection wires with almost the same number of CLBs. However, assigning optimization priority to interconnections thereby compromises the performance (delay) of the CLB network, yielding a trade-off loss of 15% worse performance than the approximately optimal performance result as determined by DAG-map.

We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables (LUTs) and can yield optimal solutions. The connections between LUTs of a logic block are modeled by virtual switches, which define a set of multiple-LUT blocks (MLBs) called an MLB-basis. We identify the MLB-bases for various commercial logic blocks. Given a n MLB-basis, we formulate FPGA mapping as a mixed integer linear programming (MILP) problem to achieve both the generality and the optimality objectives. We solve the MILP models using a general-purpose MILP solver, and present the results of mapping some ISCAS.85 benchmark circuits with a variety of commercial FPGAs. Circuits of a few hundred gates can be mapped in reasonable time using the MILP approach directly. Larger circuits can be handled by partitioning them prior to technology mapping. We show that optimal or provably near-optimal solutions can be obtained for the large ISCAS.85 benchmark circuits using partitions defined by their high-level functions.

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Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of the patch, or the wires connecting spare cells are too long, thus causing timing violations and routing congestion. In this paper, we propose a resource-aware functional patch generation approach by gate count and wiring cost estimations. In particular, we estimate the number of spare cells required by a patch and define a cost of wire length on it, which considers the physical location of the patch and a set of nearby spare cells. As a result, the patch with minimal wiring cost instead of minimal size is produced. The experiments are conducted on nine industrial testcases. These testcases reflect real problems faced by designers, and the results show our method is promising.

In mining, hazards causing rib and roof fall accidents generally develop with time. The development of a hazard depends on factors like geology, excavation geometry, overburden stress, and mining-induced stresses. Hazard mapping in an underground mine is essential for roof and rib stability assessment. However, often it is neither practical nor economical to inspect and map vast areas of mine workings with limited personnel. New technologies, recently, have been adopted in the mining industry that can solve this problem. Advances in LiDAR technology and simultaneous localization and mapping (SLAM) algorithms have led to the development of portable and mobile laser scanning devices that can be used in GPS-denied environments. Mapping with a LiDAR produces point-clouds, which are essentially sets of three-dimensional point coordinates (X, Y, Z) and point attributes. One of those attributes is the intensity values, which are just the returning light pulse that the scanner registers when the pulse is reflected from a surface. Intensity values are related to the color of a surface, so if it’s darker, reflected signal values are closer to zero, while lighter surfaces reflect higher values. In any underground mining operation, the identification of the changes in lithologies is important to assess the stability of the pillar ribs or tunnel walls. It is also important to recognize rib/roof/floor deformation or any changes i.e., fall of rocks, to recognize potential hazards. In this research, it was demonstrated that SLAM-based LiDAR or other active remote sensing sensors can be used to recognize the changes in the lithology and deformation in underground operations. In this thesis, first, the potential of identifying different lithologies with a SLAM-based LiDAR was studied. For that purpose, scans of rock cores of different lithologies were collected to investigate the relationship between the lithology, the intensity values and the measurement distance. The LiDAR data was processed with Cloud Compare, and One-Way ANOVA was used to compare the intensity values obtained for each lithology. The results showed that the intensity values of different lithologies tested in this research are statistically significantly different from each other, so the lithologies could be classified in confidence intervals of intensity values. Second, the experimental underground coal mine section was mapped with the SLAM-based LIDAR to investigate the potential of detecting changes in underground entries such as volumetric changes due to rockfalls or deformations. The collected data was processed with two algorithms: Iterative closest point (ICP) to align

Due to increasing integrated circuit design complexity, engineering change orders (ECOs) have become a necessary technique to resolve late-found functional errors and/or performance deficiencies. To fix timing violations, gate sizing and buffer insertion are commonly used in postmask ECO. These techniques, however, may not be powerful enough, especially when spare cells are inserted to balance between functional and timing repair capabilities. We propose a postmask ECO technique, called TRECO, to remedy timing violations based on technology remapping, which also supports functional ECO. Unlike conventional technology mapping, TRECO performs technology mapping with respect to a limited set of spare cells and confronts dynamic changes of wiring cost incurred by selection of different spare cells. With a precomputed lookup table of representative circuit templates, TRECO iteratively performs technology remapping to restructure timing critical subcircuits until no timing violation can be further removed. Experimental results on five industrial designs show the effectiveness of TRECO in ECO timing optimization and in timing-aware functional ECO.

Energy optimization for high-capacitance on-chip buses has become a critical problem in VLSI design, especially for embedded or SoC systems. Coupling effects between bus wires make this issue even more urgent. Coding schemes have been proposed to reduce the energy dissipation. However, the circuits overhead increases significantly when the coding schemes consider the inter-wire capacitances. In this paper, we present a novel method for energy optimization in memory address bus (MAB). The data on application specified MAB has different characters to the data bus, which has high repetition vectors and unevenly distributed switch activity. Thus a combined method is proposed to optimize the energy consumption by both self capacitance and inter-wire capacitance. First, we lower the switch activity by an efficient coding scheme. Based on the statistical data, a modified bus-invert coding scheme can intelligently divide bus lines into groups and apply bus-invert coding. It brings ultra-low area or timing penalty because of the simple circuit structure. Then the energy consumption of coupling capacitances is optimized by net reordering technique. Implemented with table-look-up technique, a fast simulated annealing algorithm is proposed to solve the net reordering problem. The experimental results show that our combined method is very efficient to reduce the energy consumption in memory address bus for varieties of applications.

Power consumption has become a great concern for IC and system designs. As a consequence, power-driven technology mapping has attracted several research attentions. However, the power model they used cannot properly capture the power dissipation when the output of a gate does not switch. In this paper, we propose a pattern oriented power modeling for improved technology mapping. We first perform a profitability study using the complete pattern to pattern transition data organized in tabular form. Then, we propose a probability-based, pattern oriented technology mapping method. Empirical results on benchmark circuits demonstrate the proposed method delivered an average of 13% power reduction compared to the traditional mapping method.

Programmable devices containing lookup tables (LUTs) and programmable logic arrays (PLAs) provide a heterogeneous target platform for user designs. Present commercial tools, which target these hybrid devices, require hand partitioning of user designs to isolate logic for each type of logic resource. In this paper, an automated technology mapping tool, hybridmap , is presented that identifies design logic partitions as suitable for either LUT or PLA implementation. A breadth-first search-based subgraph extraction and evaluation heuristic is integrated with product term (Pterm) count, area, and delay estimators to guide the technology mapping process. Hybridmap can be adapted to target a variety of PLA architectures and can accommodate user-provided timing constraints. It is shown that when timing constrained, hybridmap reduces LUT consumption for Apex20KE devices by 8% and when unconstrained by 14% by migrating logic from LUTs to Pterm structures. Hybridmap is shown to outperform previous mapping approaches for Apex20KE-type devices by up to 22%.