A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

ABSTRACTThe aim of this study was to determine concentrations of particulates and volatile organic compounds (VOCs) emitted from 3D printers using polylactic acid (PLA) filaments at a university workroom to assess exposure and health risks in an occupational setting. Under typical-case (one printer) and worst-case (three printers operating simultaneously) scenarios, particulate concentration (total and respirable), VOCs and formaldehyde were measured. Air samples were collected in the printing room and adjacent hallway. Size-resolved levels of nano-diameter particles were also collected in the printing room. Total particulate levels were higher in the worst-case scenario (0.7 mg/m3) vs. typical-case scenario (0.3 mg/m3). Respirable particulate and formaldehyde concentrations were similar between the two scenarios. Size-resolved measurements showed that most particles ranged from approximately 27 to 116 nm. Total VOC levels were approximately 6-fold higher during the worst-case scenario vs. typical situation with isopropyl alcohol being the predominant VOC. Airborne concentrations in the hallway were generally lower than inside the printing room. All measurements were below their respective occupational exposure limits. In summary, emissions of particulates and VOCs increased when multiple 3D printers were operating simultaneously. Airborne levels in the adjacent hallway were similar between the two scenarios. Overall, data suggest a low risk of significant and persistent adverse health effects. Nevertheless, the health effects attributed to 3D printing are not fully known and adherence to good hygiene principles is recommended during use of this technology.

<p>The aim of this study was to determine concentrations of particulates and volatile organic compounds (VOCs) emitted from 3D printers using polylactic acid (PLA) filaments at a university workroom to assess exposure and health risks in an occupational setting. Under typical-case (one printer) and worst-case (three printers operating simultaneously) scenarios, particulate concentra- tion (total and respirable), VOCs and formaldehyde were measured. Air samples were collected in the printing room and adjacent hallway. Size resolved levels of nano-diameter particles were also collected in the printing room. Total particulate levels were higher in the worst-case scenario (0.7 mg/m3) vs. typical-case scenario (0.3 mg/m3). Respirable particulate and formaldehyde con- centrations were similar between the two scenarios. Size-resolved measurements showed that most particles ranged from approximately 27 to 116 nm. Total VOC levels were approximately 6-fold higher during the worst-case scenario vs. typical situation with isopropyl alcohol being the predominant VOC. Airborne concentrations in the hallway were generally lower than inside the printing room. All measurements were below their respective occupational exposure limits. In summary, emissions of particulates and VOCs increased when multiple 3D printers were operating simultaneously. Airborne levels in the adjacent hallway were similar between the two scenarios. Overall, data suggest a low risk of significant and persistent adverse health effects. Nevertheless, the health effects attributed to 3D printing are not fully known and adherence to good hygiene principles is recommended during use of this technology. </p>

In this paper, we first propose a huddle-based distributed-register architecture (HDR architecture), an island-based distributed-register architecture for multi-cycle interconnect communications where we can develop several energy-saving techniques. Next, we propose an energy-efficient high-level synthesis algorithm for HDR architectures focusing on multiple supply voltages. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which is composed of functional units, registers, controller, and level converters, are very naturally generated using floorplanning results. By assigning high supply voltage to critical huddles and low supply voltage to non-critical huddles, we can finally have energy-efficient floorplan-aware high-level synthesis. Experimental results show that our algorithm achieves 45% energy-saving compared with the conventional distributed-register architectures and conventional algorithms.

The advantage of Evolvable Hardware (EHW) over traditional hardware is its capacity for dynamic and autonomous adaptation, which is achieved through by Genetic Algorithms (GAs). In most EHW implementations, these GAs are executed by software on a personal computer (PC) or workstation (WS). However, as a wider variety of applications come to utilize EHW, this is not always practical. One solution is to have the GA operations carried out by the hardware itself, by integrating these together with reconfigurable hardware logic like PLA (Programmble Logic Array) or FPGA (Field Programmable Gate Array) on to a single LSI chip. A compact and quickly reconfigurable EHW chip like this could service as an off-the-shelf device for practical applications that require on-line hardware reconfiguration. In this paper, we describe an integrated EHW LSI chip that consists of GA hardware, reconfigurable hardware logic, a chromosome memory, a training data memory, and a 16-bit CPU core (NEC V30). An application of this chip is also described in a myoelectric artificial hand, which is operated by muscular control signals. Although, work on using neural networks for this is being carried out, this approach is not very promising due to the long learning period required for neural networks. A simulation is presented showing that not only is the EHW performance slightly better than with neural networks, but that the learning time is considerably reduced.KeywordsInput PatternUniform CrossoverMyoelectric SignalReconfigurable HardwareGenetic Algorithm ProgramThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Describes a parallel-processor LSI chip (the Integrated Memory Array Processor, IMAP) and a compact real-time vision system (RVS-2). The IMAP integrates 64 8-bit processors, which operate in a SIMD manner, and 2-Mbit image memory on a single chip, and has peak performance of 3.84 GIPS. The RVS-2 consists of 8 IMAPs, a video interface, a control LSI chip (the Real-time Vision System Controller, RVSC) and a host workstation. RVSC is a 16-bit processor which carries out global data operations as well as providing an instruction stream to IMAP processors. In the RVS-2 system, the IMAP processors accomplish data-parallel operations, the RVSC applies global data operations to the results, and the host workstation carries out higher-level recognition tasks using the results obtained by the IMAPs and the RVSC. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing is carried out in 0.1 to 0.7 ms, which is 50 to 300 times faster the video rate.

Presented in this paper is a feasibility study of a chip stacking technology for very high bandwidth communication. This technology utilizes transmission line coupling between coplanar differential lines constructed in metal layers of two chips placed facing each other such that the differential pairs are overlapped with a spacing of many microns. In previous study we demonstrated communication at 12.5 GHz between two differential pairs of transmission lines fabricated on different metal layers in a single chip. As the next step of the study, we developed the second test chip to demonstrate actual communication between two LSI chips using this technology. The test chip includes a high-speed hysteresis-type receiver that extracts the original digital signals from differentiated signals result from the coupling region. In this chip, effect of AC coupling capacitors placed between the driver output and the transmission-line-coupling region in order to reduce power consumption can be also investigated. Evaluation of the second test chip is in progress.

WASMII is a virtual hardware system that executes dataflow algorithms. It is based on an MPLD (Multifunction Programming Logic Device), an extended FPGA (Field Programmable Gate Array) that implements multiple sets of functions as configurations of a single chip. An algorithm to be executed on WASMII is written in the DFC dataflow language and then translated into a collection of FPGA configurations, each representing a page-sized subgraph of the dataflow graph. Although we have developed an emulation system and software environment for WASMII, it has tended to be an unrealistic system due to the difficulty of the MPLD implementation. However with recent technologies of semiconductors, FPGA and DRAM can be implemented into a single LSI chip. By using the column buffer of the DRAM array as a configuration memory of an FPGA, replacement of configuration data can be done almost the same speed as an MPLD. Compared with the MPLD approach, a large amount of data can be stored in the integrated DRAM. Initial simulation results show that such a chip can almost save the loss caused by data transfer from the off chip memory of original WASMII.

A method of path-limitation is proposed for the efficient DP matching of spoken words. Results of a preliminary recognition experiment show that this method can reduce the recognition errors as well. A method for effective speaker normalization is proposed. This method is based on the transformation of the relative positions of the five vowels of a given speaker in the parameter space. As a result of transformation, the dimension of the parameter space is reduced by a factor of four, yielding a great advantage in the computation time for matching. A study on the realization of a spoken-word recognition device using systolic array processors is described. A cyclic configuration that permits real-time matching of 600 templates with a single LSI chip is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Recent advances in the field of infrared focal planes provide the detector array technology needed to manufacture monolithic and hybrid detector arrays containing large numbers of detectors with buffer amplifiers and multiplexing on a single LSI chip. Infrared focal planes of the future will require the integration of these detector/multiplexer arrays together with support electronics into a manufacturable, testable, reliable, and maintainable IFPA. The IFPA must efficiently interface with cryogenic systems, optics, mechanical structures, and signal processing electronics. Hughes Aircraft Company has conducted a study to determine what technologies are needed to support the assembly of large infrared focal planes. This paper discusses the results of this IFPA study and the progress being made in developing such technologies. Cyrogenic chip carriers, high-density electrical interconnects, multilayered electrical interconnects, and high-density cables are discussed in terms of an architectural approach as it relates to the manufacture, test, and assembly of IFPAs. An integrated focal plane array design is presented to exemplify the validity of this IFPA design approach. The example IFPA design includes, identification of critical test methodologies, assembly techniques, and electrical interconnect requirements that will challenge the state of the art of focal plane assembly and manufacture. Large IFPAs of the next decade will pose new challenges in focal plane architecture, cryogenic high-density cables, and electrical interconnects as well as in cryogenic thermal design and test. This paper presents a modular IFPA design approach that provides solutions to these challenges.© (1980) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

One of the major subsystems of the central processor unit is the arithmetic logic unit (ALU) in which the binary operations of addition, subtraction, multiplication, and division are performed. All arithmetic functions can be related to addition: subtraction is performed by adding complemented numbers, multiplication by some form of repeated addition, and division by repeated subtraction. Thus in all these functions the basic arithmetic element is the binary adder. Consequently, the ALU consists of a number of registers which contain the operands, intermediate and final results, a basic adder (working in pure binary or binary-coded decimal) and a control unit. All these functions, including memory, can be obtained on a single LSI chip.

In this paper, an implementation of concurrent backoff delay process on a single chip with IEEE 802.15.4 hardware and 8051 processor core that can be used for analyzing the interference on IEEE 802.15.4 channels due to WiFi traffics is studied. The backoff delay process of IEEE 802.15.4 CSMA-CA algorithm is explained. The characteristics of random number generator, timer, and CCA register included in the single chip are described with their control procedure in order to implement the process. A concurrent backoff delay process to evaluate multiple IEEE 802.15.4 channels is proposed, and a method to service the associated tasks at sequentially ordered backoff delay events occurring on the channels is explained. For the implementation of the concurrent backoff delay process on a single chip IEEE 802.15.4 hardware, the elements for the single channel backoff delay process and their control procedure are used to be extended to multiple channels with little modification. The medium access delay on each channel, which is available after execution of the concurrent backoff delay process, is displayed on the LCD of an IEEE 802.15.4 channel analyzer. The experimental results show that we can easily identify the interference on IEEE 802.15.4 channels caused by WiFi traffics in comparison with the way displaying measured channel powers.

Finite impulse response (FIR) filtering is a ubiquitous operation in digital signal processing systems and is generally implemented in full custom circuits due to high-speed and low-power design requirements. The complexity of an FIR filter is dominated by the multiplication of a large number of filter coefficients by the filter input or its time-shifted versions. Over the years, many high-level synthesis algorithms and filter architectures have been introduced in order to design FIR filters efficiently. This article reviews how constant multiplications can be designed using shifts and adders/subtractors that are maximally shared through a high-level synthesis algorithm based on some optimization criteria. It also presents different forms of FIR filters, namely, direct, transposed, and hybrid and shows how constant multiplications in each filter form can be realized under a shift-adds architecture. More importantly, it explores the impact of the multiplierless realization of each filter form on area, delay, and power dissipation of both custom (ASIC) and reconfigurable (FPGA) circuits by carrying out experiments with different bitwidths of filter input, design libraries, reconfigurable target devices, and optimization criteria in high-level synthesis algorithms.

Animal waste contains high numbers of microorganisms and therefore can present a potential biological threat to human health. During episodic rainfall events resulting in runoff, microorganisms in the waste and soil may migrate into surface runoff, contaminating surface water resources. A probabilistic human exposure (HE) model was created to determine exposure to faecal indicator bacteria (FIB): total coliforms (TC), E. coli and enterococci following application of bio-based fertiliser (dairy cattle slurry, digestate) to grassland; using a combination of experimental field results and literature-based data. This step was followed by a quantitative microbial risk assessment (QMRA) model for pathogenic E. coli based on a literature-based dose-response model. The results showed that the maximum daily HE (HEdaily) is associated with E. coli for unprocessed slurry (treatment T1) on day 1, the worst-case scenario where the simulated mean HEdaily was calculated as 2.84 CFU day −1. The results indicate that the overall annual probability of risk (Pannual) of illness from E. coli is very low or low based on the WHO safe-limit of Pannual as 10 −6. In the worst-case scenario, a moderate risk was estimated with simulated mean Pannual as 1.0 × 10 −5. Unpasteurised digestate application showed low risk on day 1 and 2 (1.651 × 10 −6, 1.167 × 10 −6, respectively). Pasteurised digestate showed very low risk in all scenarios. These results support the restriction imposed on applying bio-based fertiliser if there is any rain forecast within 48 h from the application time. This study proposes a future extension of the probabilistic model to include time, intensity, discharge, and distance-dependant dilution factor. The information generated from this model can help policymakers ensure the safety of surface water sources through the quality monitoring of FIB levels in bio-based fertiliser.

Most Internet worms use random scanning. The distribution of vulnerable hosts on the Internet, however, is highly non-uniform over the IP-address space. This implies that random scanning wastes many scans on invulnerable addresses, and more virulent scanning schemes may take advantage of the non-uniformity of a vulnerable-host distribution. Questions then arise how attackers may make use of such information, and how virulent the resulting worm may be. These issues provide "worst-case scenarios" for defenders and "best-case scenarios" for attackers if the vulnerable-host distribution is available. This work develops such a scenario as the so-called importance scanning. Importance scanning results from importance sampling in statistics that scans IP-address space according to an empirical distribution of vulnerable hosts. An analytical model is developed to relate the infection rate of worms with the importance-scanning strategies. Experimental results based on parameters chosen from code red and slammer worms show that an importance-scanning worm can spread much faster than both a random-scanning worm and a routing worm. Furthermore, a game-theory approach suggests that the best strategy for defenders is to scatter applications uniformly in the entire IP-address space.

While technology scaling enables the mass integration of transistors into a single chip for performance enhancement, it also makes processors less reliable with ever-increasing failure rates. In this paper, we study the problem of energy minimization for scheduling periodic fixed-priority applications on multiprocessor platforms with fault tolerance requirements. We first introduce an efficient method to determine the checkpointing scheme that guarantees the schedulability of an application under the worst-case scenario, i.e. up to K faults occur, on a single processor. Based on this method, we then present a task allocation scheme aiming at minimizing energy consumption while ensuring the fault tolerance requirement of the system. We evaluate the efficiency and effectiveness of our approaches using extensive simulation studies.