A Refined Phase Estimation Based Parallel Carrier Recovery Algorithm in High Speed Wireless Communication Systems

The paper emphasizes on the analysis on wideband channel model for high speed wireless communication systems. The research problem in this study are based on the following concepts such as (i) Firstly, it is necessary to change to the appropriate physical devices that can support 5G system, (ii) It is required to design a channel that will adapt to the medium that will be convenient for the changed physical devices, and (iii) Mobile terminals that currently use 4G cannot be used in 5G system. The objectives in this study are - to analyze the existing channel model for mobile communication, to analyze the mathematical and dynamical model for wireless propagation channel, to implement the wireless propagation channel with specific purposes, to implement the optimized channel model performance, and to evaluate the performance of the developed channel design. The numerical analyses in this study are conducted by using MATLAB language. The research direction in this study are based on the channel system functions, and tapped delay-line models. The simulation results are confirmed that the 12 taps in this study for the high speed wireless communication system design.

The conventional DPLLs (digital phase-locked loops) are designed for Gaussian noise environment, and play important roles in carrier and clock recoveries. However, in power line communication (PLC), the power line noise is often impulsive, and then its statistical feature is different from Gaussian one. Therefore, we introduced class A noise model in PLC first, and then proposed an optimum DPLL for such class A noise environment using the techniques based on MAP (maximum a posteriori) estimating. The simulated results show the proposed DPLL has the smaller steady state phase errors than the conventional DPLL under class A noise environment.

A detailed and realistic time-varying channel model is used in the simulation of a 20-Mbps indoor wireless communication system that uses a DFE on the reverse link and a Tomlinson-Harashima (1971, 1972) precoder on the forward link to mitigate ISI. The motivation of such an asymmetric scheme is to minimize the hardware complexity of the portable unit. Results confirm the viability of this system by quantifying the performance of the forward link as a function of time, portable speed, channel delay spread, transmission distance and training duration. Additionally, a simple and effective scheme for receiver AGC at the portable is proposed and evaluated.

Data partitioning algorithms aiming to minimize the execution time and the energy of computations in self-adaptable data-parallel applications on modern extreme-scale multicore platforms must address two critical challenges. First, they must take into account the new complexities inherent in these platforms such as severe resource contention and non-uniform memory access. Second, they must have low practical runtime and memory costs. The sequential data partitioning algorithms addressing the first challenge have a theoretical time complexity of O( $m * m * p * p$ ) where $m$ is the number of points in the discrete speed/energy function and $p$ is the number of available processors. They, however, exhibit high practical runtime cost and excessive memory footprint, therefore, rendering them impracticable for employment in self-adaptable applications executing on extreme-scale multicore platforms. We present, in this paper, the parallel data partitioning algorithms that address both the challenges. They take as input the functional models of performance and energy consumption against problem size and output workload distributions, which are globally optimal solutions. They have a low time complexity of O( $m * m * p$ ) thereby providing a linear speedup of O( $p$ ) and low memory complexity of O( $n$ ) where $n$ is the workload size expressed as a multiple of granularity. They employ dynamic programming approach, which also facilitates the easier integration of performance and energy models of communications. We experimentally study the practical cost of application of our algorithms in two data-parallel applications, matrix multiplication and fast Fourier transform, on a cluster in Grid’5000 platform. We demonstrate that their practical runtime and memory costs are low making them ideal for employment in self-adaptable applications. We also show that the parallel algorithms exhibit tremendous speedups over the sequential algorithms. Finally, using theoretical analysis for a forecast exascale platform, we demonstrate that the parallel algorithms have negligible execution times compared to the matrix multiplication application executing on the platform.

Parallel algorithms developed for CAD problems today suffer from three important drawbacks. First, they are machine specific and tend to perform poorly on architectures other than the one for which they were designed. Second, they cannot use the latest advances in improved versions of the sequential algorithms for solving the problem. Third, the quality of results degrade significantly during parallel execution. We address these three problems for an important CAD application: standard cell placement. We have developed a parallel placement algorithm that is portable across a range of MIMD parallel architectures. The algorithm is part of the ProperCAD project which allows the development and implementation of a parallel algorithm such that it can be executed on a wide variety of parallel machines without any change to the source. The parallel placement algorithm is based on an existing implementation of the sequential simulated annealing algorithm, TimberWolfSC 6.0 (C. Sechen and A. Sangiovanni-Vincentelli, 1985).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Time-Interleaved Analog-to-Digital Converter (TIADC) is a promising approach to meet the requirement of high speed wireless communication systems. However, mismatches between the channels of TIADCs generate unwanted distortions at the output spectrum. This paper demonstrates a fully digital background calibration technique to identify and compensate three all deviations which are offset, gain and timing mismatches for TIADCs. In which, offset mismatch is corrected by computing the average of the output samples of each channel. The gain and timing mismatches are compensated by using LMS algorithm and the modulation matrix m[n]. The simulation results show that the performance of the ADC is improved by 41.32 dB for SNDR and 64.6 dB for SFDR.

Block Data Transmission Systems (BDTS) are used in high speed wireless communication systems with time dispersive channel characteristics. Since Maximum Likelihood Block Detection (MLBD) requires huge amount of computation, Sphere Detection (SD) technique has been introduced as an alternative. This paper proposes an An Lattice Sphere Detection (AnLSD) technique for detection in block data transmission systems (BDTS). The An lattice structure offers more dense constellation points than the customary Zn lattice in SD technique. Thus, the proposed AnLSD uses An lattice generator matrix as the channel matrix, and uses the Gram matrix which is obtained from the generator matrix as part of the detection process. Simulation results show that the proposed AnLSD performs very close to the Exhaustive search (ES) using block size of 20 bits. It is also performing better than the other renowned methods tested under a channel with spectral nulls. The proposed AnLSD technique offers significant reduction in term of objective functions evaluation as compared to the other renowned methods.

Summary form only given, as follows. Commercial communications systems are rapidly expanding to the RF and millimeter-wave spectrum. The impacts of recent advances in the Ill-V compound semiconductor devices and integrated circuits on modern high speed wireless communications systems will be illustrated in a prototype microwave communication link.

Spatio-temporal equalization is a technique which utilizes both spatial and temporal information of the received signal to compensate for intersymbol interference due to multipath fading. Considering the application of a spatio-temporal equalizer to high speed wireless communications systems, such as wireless LANs, this paper proposes a new spatio-temporal equalization method using a cascade configuration of an adaptive array and a DFE (decision feedback equalizer), which can be realized with small number of weights, and hence, low computational complexity. However, it has to pay a price for the simplicity, namely, the error performance surface becomes a fourth-order function of the weights, and possibly has two minima. In order to avoid a wrong trap by a local minimum during the adaptation of the MMSE (minimum mean-squared error) based adaptation algorithm with any initial values, the proposed equalizer calculates the weights of the adaptive array and the DFE separately in two steps, and the adaptive array selects a path or paths to capture depending on channel conditions. Computer simulation results show that the proposed method can achieve good performance in various channel models, which are based on measurement reports, in low computational complexity.

Frequency selective fading effects in OFDM based high speed wireless communication systems can be highly mitigated by using adaptive antenna arrays. In addition, the use of discrete wavelet transform (DWT) processing in OFDM systems can successfully counter the degrading effect of inter symbol interference (ISI) without the need of cyclic prefix (CP), and hence conserves band width and improves the spectral efficiency. In this paper, an OFDM system utilizing DWT based least mean square (LMS) adaptive beamformer is considered. The use of the wavelet transform reduces the signal space dimension and hence results in low complexity in addition to data denoising. Time saving in signal beamforming processing can be achieved by using different levels of decomposition in the wavelet transform, with acceptable accuracy. Theoretical analysis and computer simulations demonstrate how the suggested scheme, with different wavelet families and different decomposition levels, achieves better beamforming performance with faster convergence, as compared to conventional adaptive beamforming.

Carrier recovery is an important building block for modern coherent optical communication systems. This chapter first introduces the concept of carrier recovery and the challenges faced. Before diving into the detail of hardware‐efficient carrier recovery algorithms, the chapter gives a brief introduction to the Cramer‐Rao lower bound (CRLB), CRLB provides us with a more fundamental way to evaluate the effectiveness of various carrier recovery algorithms. Before proceeding to discuss various frequency offset estimation schemes, the chapter focuses on several hardware‐efficient phase estimation algorithms by assuming that the frequency offset has been largely compensated‐for before phase recovery. It describes in more detail three hardware‐efficient multistage phase recovery algorithms that have been demonstrated for high‐SE 100Gb/s and beyond transmission experiments. These are the multistage hybrid blind phase search (BPS)/maximum likelihood (ML) phase recovery algorithm, the hybrid phase‐locked loop (PLL)/ML algorithm, and the training‐assisted two‐stage BPS/ML algorithm.

We propose a polarity decision carrier recovery algorithm that is useful for carrier acquisition in high order-QAM (quadrature amplitude modulation). The PD (phase detector) output and its variance characteristics are mathematically derived and the simulation results are presented. We design a carrier recovery loop with this polarity decision PD and ATC (automatic transfer-mode controller), which is proposed to detect a proper time for mode change and to yield fine phase tracking error in the steady state. While the conventional DD (decision directed) algorithm can only acquire frequency offsets of less than /spl plusmn/10 kHz, the proposed carrier recovery algorithm can acquire up to /spl plusmn/200 kHz without AFC (automatic frequency control). We show the RMS (root mean square) phase error performance using the proposed carrier recovery PLL (phase locked loop).

The process of merging two arbitrary partitions of a given finite set 𝒰 of n elements is known as coarsest refinement. In the COARSEST REFINEMENT PROBLEM we are given two arbitrary partitions 𝒳, 𝒴 of the set 𝒰 such that 𝒳 = {𝒳1, 𝒳2, ..., 𝒳 x} and 𝒴 = {𝒴1, 𝒴2, ..., 𝒴 y}, and determine a new partition 𝒵 = {𝒵1, 𝒵2, ..., 𝒵 z} such that each is a common non-empty subset of some 𝒳 a ∈ 𝒳 and some 𝒴 b ∈ 𝒴 and |𝒵| is as small as possible. This article describes a resource-efficient parallel algorithm to solve this problem. More specifically, we show that a coarsest refinement can be computed in O( t( n) + log n) parallel time using max{nlogn,p(n)} processors, where t( n) denotes the running time of a parallel stable sorting algorithm that uses p( n) processors on an EREW PRAM. This result depends on t( n) and p( n). We give a table that shows the best known time and processor complexities for a parallel stable sorting algorithm. If the parallel stable sorting algorithms by Ajtai et al., Cole, and Leighton are used, the coarsest refinement can be computed in O(log n) parallel time using n processors on an EREW PRAM. On the other hand, if the parallel stable sorting algorithm by Bahig et al. is used, the coarsest refinement can be computed in O(lognlog(nlogn)) parallel time using nlogn processors on an EREW PRAM. In addition, we show that on, a RAM machine, our parallel algorithm runs as asymptotically efficient as the fastest known sequential algorithm.

Electronic circuits: by E. J. Angelo, Jr. 450 pages, diagrams, 6 × 9 in. New York, McGraw-Hill Book Co. Inc., 1958.Price, $9.00.

The demand for highly energy-efficient circuits and systems has exponentially increased for Systems on Chip (SoC). A fractional-N phase-locked loop (PLL) is one of the most important building blocks in SoCs for a variety of applications, such as frequency synthesis for wireless transceivers and system clock generation for processors, memories, and I/O interfaces. Recent developments in fractional-N digital PLLs (DPLLs) [1]–[3] have shown great potential for achieving low-power operation and small chip area. However, none of these works have achieved power consumption below $500 \mu \mathrm {W}$ due to the number of building blocks operating at the oscillator frequency. Furthermore, the digitally controlled oscillators (DCOs) in [1]–[3] consume more than $250 \mu \mathrm {W}$ of power to achieve a good phase noise and a high-enough amplitude for DPLL locking. A digital sub-sampling architecture [1], [2], [4] can potentially reduce the overall power consumption by bypassing these high-frequency building blocks. Unfortunately, the absence of frequency acquisition makes such architecture vulnerable to sudden or large frequency disturbances. Even though a background frequency-locked loop (FLL) [1], [4] can be applied, it consumes large power due to the counter working at the DCO frequency. The typical solution to save power consumption is to turn off the FLL [2] after the PLL has been stabilized. Despite the benefit of the power reduction, a sub-sampling PLL has multiple frequency lock-in ranges near the integer multiple of the reference frequency, which could cause false locking if the frequency disturbances are within those ranges. To address the above issues, this work presents a fractional-N DPLL achieving a $265 \mu \mathrm {W}$ power consumption with robust phase and frequency acquisition with negligible power overhead in a 65nm CMOS technology. It also achieves an rms jitter of 2.8ps, which corresponds to an FoM of-236.8dB.