A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations

Embedded systems carry and process more and more sensitive information in untrusted environments, where an attacker can wiretap the external communication and also has unlimited physical access to the device. Cryptography protects systems against many of the threats and relies on the security of the cryptographic keys inside the system. Physical Unclonable Functions (PUFs) measure manufacturing variations inside integrated circuits, for example FPGAs, to generate a unique secret PUF response inside each device. Similar to deriving a biometric pattern from human features, the individual pattern inside an FPGA differs slightly from measurement to measurement. From these measurements, the PUF response is generated to derive a secure and reliable cryptographic key. The Ring-Oscillator (RO) PUF is a popular PUF type because of its high randomness and reliability. Frequencies of ROs are compared pairwise to derive one secret bit. So far, the reliability of RO PUFs was evaluated by counting bit flips in measured PUF responses. This work analyzes the distribution of frequency measurements to derive the behavior of the PUF. Analyzing the frequency distributions gives a more precise estimation of the PUF bit error rates than measuring the bit errors after the comparison of two oscillator frequencies. The evaluation of publicly available real world empirical FPGA data has shown that most error probabilities of RO PUF responses are so low that they cannot be measured in feasible time. For almost 200 evaluated FPGAs, more than 70% of the PUF outputs on every FPGA have bit error probabilities under 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-20</sup> . We can even ensure this error probability for over 60% of the PUF outputs after a practicable number of frequency measurements with a confidence of 99.9%. Index Terms-Physical Unclonable Functions (PUFs), Ring Oscillator PUF, FPGA, Statistics.

Physical Unclonable Function (PUF) is one of the most promising hardware features that can be utilized to improve system security. Ring Oscillator (RO) PUF captures the delay difference of a pair or a group of ROs introduced during fabrication process and defines PUF secrecy based on such difference. In this paper, we propose a framework to build RO PUF at inverter level, instead of RO level. This provides us the flexibility in choosing whether an inverter should be included in the RO-PUF and hence improve the security and reliability of RO PUF secrecy and reduce its hardware cost. Experimental results demonstrate that the PUF secrecy generated by our configurable RO PUFs is random (by passing the NIST randomness test) and unique from chip to chip. Our approach is more reliable against voltage and temperature variation than the original RO PUF and is 4X more hardware efficient than the robust 1-out-of-8 RO PUF.

Silicon based Physical Unclonable Functions (PUFs) are circuits which measure random variations of the manufacturing process to generate a secret. The quality of a PUF predominantly depends on its predictability and reliability. Available quality measures are not always sufficient and do not show the root cause for high predictability. This paper suggests entropy and joint entropy of certain views on PUFs and interprets the measures to show different design issues to a designer and to give a global measure for PUF quality. Simulation results for Arbiter PUF, Ring Oscillator PUF, and SRAM PUF are evaluated by the new measures and results for Ring Oscillator and Arbiter PUFs show how the measures can be used to guide designers.

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation.

Physical unclonable functions (PUFs) are promising hardware security primitives which are suitable for low power applications, such as the Internet of Thing (IoT). The Ring Oscillator (RO) PUF is one of the most reliable and strong PUFs. On the other hand, it consumes more power than others. The main aim of this paper is to propose a design for a low power RO-PUF. The proposed design is based on utilizing modules that consume less power than the conventional one. In the proposed design the frequency divider (FD) and the D-flipflop (DFF) are employed instead of the counters, the timer, and the comparator circuits. Evaluation results demonstrate that the proposed design can effectively reduce power consumption. The proposed PUF was designed using 20 nm FinFET technology. The proposed PUF consumes $\mathbf{264} \mu\mathbf{w}$ per challenge-response pair at supply voltage 0.9 V. The averaged reliability of the proposed design is 99.5%, over a range of temperature from -40 to 125°C and supply voltage from 0.8 V to 1 V. The proposed PUF decreases the power consumption while maintaining highperformance metrics.

Physical Unclonable Functions (PUF) are an emerging hardware security primitives proposed by various researchers in last one decade. PUFs are useful security architectures used for identification, authentication and cryptographic key generation. Many PUF topologies are proposed in the past targeting both ASIC and FPGA. It is nearly impossible to get two PUF circuits with same characteristics for the same design. PUFs make use of random process variation occurring during manufacturing of IC which is uncontrollable. The most versatile PUF is ring oscillator (RO) PUF, in which the frequencies of ring oscillators are compared to produce the PUF response. The conventional approach consumes large number of ring oscillators and requires all RO's to be mutually symmetric. In this paper, we have proposed a RO-PUF for FPGA devices, which is capable of generating multiple output bits from each ring oscillator with better security metrics in comparison with PUF designed with similar technique. The PUF is implemented on Xilinx Spartan 3E FPGA boards and the challenge-response pairs (CRP) are verified for statistical properties.

The lack of stability is one of the limitations that constrain physical unclonable function (PUF) from being put in widespread practical use. In this paper, we propose a weak PUF and a strong PUF that are both completely stable. These PUFs are called locally enhanced defectivity physical unclonable function (LEDPUF). An LEDPUF is a pure functional PUF that does not require any kinds of correction schemes as conventional parametric PUFs do. The source of randomness of an LEDPUF is extracted from locally enhance defectivity without affecting other parts of the chip. In this paper, we construct a weak LEDPUF by forming arrays of directed self-assembly random connections, and the strong LEDPUF is implemented by using the weak LEDPUF as the key of a keyed-hash message authentication code. Our simulation and statistical results show that the entropy of the weak LEDPUF bits is close to ideal, and the inter-chip Hamming distances of both weak and strong LEDPUFs are about 50%, which means that these LEDPUFs are not only stable but also unique. We develop a new unified framework for evaluating the security of PUFs, based on password security, by using information theoretic tools of guesswork. The guesswork model allows us to quantitatively compare, with a single unified metric, PUFs with varying levels of stability, bias, and available side information. In addition, it generalizes other measures to evaluate the security level, such as min-entropy and mutual information. We evaluate the guesswork-based security of some measured static random access memory and ring oscillator PUFs as an example and compare them with an LEDPUF to show that the stability has a more severe impact on the PUF security than biased responses. Furthermore, we find the guesswork of two new problems: guesswork under the probability of attack failure and the guesswork of strong PUFs that are used for authentication.

Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.

A Physical Unclonable Function (PUF) is often used to uniquely identify an integrated circuit by extracting its internal random differences using so-called Challenge Response Pairs (CRPs). As CRPs include unique information about the underlying hardware variations, PUF design is a promising approach to provide authentication and IP-protection capabilities. In this paper, an XOR-gate-based configurable Ring Oscillator (RO) PUF (denoted as XCRO PUF) is presented. This XCRO PUF can generate more CRPs compared with state-of-the-art PUF designs by using the same number of configurable logic blocks (CLBs) in an FPGA implementation. This design is implemented in the Xilinx Spartan-6 XC6SLX9 FPGAs with fixed locations for the XCROs (placed within a ring to improve its uniqueness). The XCRO PUF shows better uniqueness and reliability than other PUF designs. Moreover, a XCRO PUF consumes only 12.5% of the hardware resources to generate a 1-bit response compared with other CRO PUFs implemented in FPGA.

Silicon physically unclonable functions (PUFs) are circuits that exploit modern manufacturing variations to generate unique signatures for chip authentication and cryptographic key generation. Existing research has focused on improving PUF quality at architectural or design levels, but has ignored opportunities available during fabrication, which is the source of systematic and random variation in (ICs)/PUFs. For typical ICs (where security is not a concern), optical proximity correction (OPC) is used to suppress both these types of variations. However, several prior works have shown that only systematic variations negatively impact PUF quality and random variations are beneficial for PUFs. In this paper, we propose two PUF-aware OPC cost functions: 1) P-OPC generates a PUF lithography mask that increases all variations in PUF circuitry (the opposite of state-of-the-art OPC), and 2) SVC-OPC generates mask patterns that reduce the systematic variation found in PUFs for better quality. Simulation results for ring oscillator (RO) PUFs show that the proposed techniques can improve PUF signature quality compared to current state-of-the-art OPC.

Physically Unclonable Function (PUF) designs proposed in the recent literature vary widely in diverse characteristics such as hardware resource requirement, reliability, entropy, and robustness against mathematical cloning. Most of the standalone PUF designs suffer from either poor performance profile or unacceptable resource-overhead. We present a novel PUF design paradigm, termed as PUF Composition, that utilizes smaller PUFs as design building blocks to define a “Composite PUF” having larger challenge-space and superior performance profile at reasonable resource-overhead. A formal framework for PUF composition based on a probabilistic model has also been developed to enable the Composite PUF designer to have a-priori estimate of the relative qualities of several composite PUF options, without actually implementing them physically. The notion of PUF composition, and the probabilistic model developed for delay-PUFs, have both been validated using Ring Oscillator PUF (ROPUF) and Arbiter PUF (APUF) on Xilinx Spartan-3 Field Programmable Gate Array (FPGA).

Field Programmable Gate Arrays (FPGAs) accelerate the expansion of the Internet of Things by enabling seamless device integration, energy efficiency, low latency, and high determinism, thanks to their reconfigurability feature. However, FPGAs must be protected against various security threats to guarantee intended operation. Physically Unclonable Functions (PUFs), which utilize a device’s intrinsic physical properties, have become a robust security primitive that overcomes the limitations of conventional security solutions. This work proposes a lightweight, platform-independent Ring Oscillator (RO) PUF that adapts the cross-platform RO PUF (CPRO PUF) technique. Its main goal is to minimize the hardware footprint and improve resource efficiency by optimizing the use of various logic components. The proposed PUF has been implemented and validated on Xilinx Artix-7 (28 nm) and Spartan-6 (45 nm) FPGAs. In comparison with earlier studies, the obtained results show improvements in resource utilization, reliability, uniqueness, and uniformity, while ensuring the intended security.

Physically Unclonable Functions (PUFs) are becoming more widely recognized as tamper-resistant, high-entropy hardware security primitives. Leveraging the intrinsic manufacturing properties of integrated circuits, PUFs provide a lightweight, cost-effective technique for device identification and cryptographic key generation. Despite the existence of various PUF designs and architectures, the ring oscillator (RO) PUF stands out as one of the most notable. This significance is due to its simplicity of implementation and outstanding performance metrics. However, traditional RO-PUFs are often classified as weak PUFs because they support a limited size of input-output combinations. This paper introduces a configurable inversion unit designed to construct a lightweight, robust architecture configurable (RAC) RO-PUF. The proposed unit comprises an XOR gate, an XNOR gate, and a multiplexer. The RACRO-PUF significantly increases the size of generated output bits while efficiently utilizing minimal hardware resources. The performance of the RACRO-PUF stands out in evaluations, recording a uniqueness of 49.78 %, uniformity of 49.42 %, reliability of 97.72 %, and impressive randomness of 98.34 %.

A novel configurable ring oscillator PUF with improved reliability using reduced supply voltage

Physically Unclonable Functions (PUFs) are new hardware solution for low cost and secure communication primitives such as hardware authentication and secure key generation. PUFs use the random properties of a device to produce unique data. Ring Oscillator PUFs (RO PUF) are one of the most applicable PUFs because of its good reliability and easy implementation on FPGAs. One major problem of Ro PUFs is limited Challenge-Response pairs number. We consider this problem and introduce a new architecture of RO PUF that increases Challenge-Response pairs of a typical PUF with using minimum resources. In our architecture, we use an XOR gate to prevent direct response disclosure and increase our response unpredictability. In this manner, we increase Challenge-Response pairs up to (n(n - 1))/2. We also show the result of the unity and uniqueness of our proposed PUF by implementing 110 PUFs on five XC3S400 FPGAs.