1- https://doi.org/10.1007/978-981-13-3113-8_3
A Reusable Functional Simulation Verification Method Based on UVM for FPGA Products in DAS
- Jan 1, 2019
- Xiu-Hong Lv +4 more
Functional simulation verification is an important part for Field Programmable Gate Array (FPGA) product verification. Many problems had been encountered in FPGA verification in nuclear instrument control system when adopting traditional verification methods, such as long verification cycle, poor reusability of verification testbench, low level of automation, etc. Universal Verification Methodology (UVM) has the characteristics of reusability, extensibility and automatic. We introduced UVM for FPGA verification, which improved the efficiency and quality of verification process, and saved the project time. At present, this technology had been applied in the IO product verification of Diverse Actuation System (DAS) and achieved good results, and this approach will be applied gradually in the project.
- # For Field Programmable Gate Array
- # Universal Verification Methodology
- # Low Level Of Automation
- # Functional Simulation Verification
- # Verification Cycle
- # Product Verification
- # Functional Verification
- # Functional Verification Method
- # Verification Method
- # Reusable Verification
