A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks

Verification of softwarehardware hybrid systems is difficult because of the inter process communication, concurrency and synchronization and the configuration of processors. Multi-Processor Systems on Chip (MPSoC) are examples of such hybrid systems, targeted for embedded systems. We focus on the verification of MPSoC software (application running on MPSoC) and the system consisting of the application running on the MPSoC platform. We aim at generating test cases for verifying the software while overcoming the limitations of previous approaches. Metaheuristic approaches get blocked in local optima and constraint programming approaches are slow on complex programs, to satisfy given coverage criteria. We propose to combine metaheuristic and constraint programming solvers in a novel way: executing both the solvers sequentially and splitting and reducing the individual input variable domains. We also propose to generate test cases from the functional test objectives to check the proper functioning of the software running on the hardware platform. We report the results of the preliminary experiments.

The progressive maturity of VLSI manufacturing technology is helping in integrating more and more processing elements and memory units on a single die to form a Multiprocessor System-On-Chip (MPSoC). Network-on-Chip (NoC) is adopted as communication backbone for most of these modern day multiprocessor systems. As complexity of these system scales, there has been a growing concern on the dependability of these processing and communication elements. In this paper, we propose a centralized hardware fault-tolerant network interface (NI) for NoCs based on spatial division multiplexing. Experiments show that the proposed design has better throughput than a non fault-tolerant design with only 18% area overhead. We also introduce an area optimized distributed fault-tolerant NI architecture which provides 50% more throughput than the centralized design for high fault rates.

The performance of a multiprocessor system-on-chip (MPSoC) is not only dependent on the computational capabilities of on-chip processors but also depends on the communication medium connecting them. This has shifted the emphasis from computation to communication architectural design. In this paper, a dynamically reconfigurable network-on-chip (NoC) architecture has been proposed for reconfigurable MPSoC, as a solution to the increased communication needs, keeping low power, quality of service (QoS) and scalability of network in mind

With technology scaling, Multiprocessor System on Chip (MPSoC) which consist of multiple processors connected via a Network on Chip (NoC) have become prevalent. Applications are mapped to MPSoC's by representing it in the form of a task graph. Task scheduling involves mapping task to processor cores so as to meet the deadline. For a given deadline, slack at each node is defined by the amount of time by which a task execution can be delayed without missing the deadline. With increase in the number of cores and high application parallelism, NoC is becoming a bottleneck due to the presence of large number of concurrent communications. Increasing network resources (links and routers) reduces the communication time but the area and power goes up. In this paper we present an application aware heuristic to synthesize a minimal network connecting a set of cores in an MPSoC in the presence of hard deadlines. Our approach is based on modeling communication between a pair of processors as tasks known as “Comtasks”. The network is generated by “scheduling” these comtasks onto a set of routers so as to obtain a network with minimum area which fills up the available slack. Moreover, we also identify the set of overlapping comtasks and generate a minimal network to allow the maximum set of overlapping comtasks to execute concurrently. We compared our approach with a greedy network generation heuristic and the results show 80% benefit in the router area.

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Network on Chips (NoC) become the preferred on-chip communication platform for current and future SoC architectures. In this paper, we present the design of a new on chip network with Quality-of Service (QoS) support. The proposed routers use new dynamic arbitration architecture with a priority-based scheduler to differentiate between multiple packets with various QoS requirements. A wormhole input queued 2-D mesh router was created to verify the capability of our router. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology, with different flit size. Finally, a performance study in terms of average latency and throughput of 4×4 mesh 2-D network was conducted to prove the benefit of using the QoS packets and finding the saturation point.

As there is a rapid growth in use of consumer embedded products from past decade, new tendencies forecast highly the usage of heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. As MPSoCs are made up of hundreds of cores, Intercommunication requirements will not be feasible using a single shared bus or a hierarchy of buses due to their poor scalability with system size, and the different components are designed by various vendors, their shared bandwidth between all the attached cores and the energy efficiency requirements of final products. To overcome the above said problems of scalability and complexity, Networks-On-Chip (NoCs) have been proposed as a promising replacement to eliminate many of the overheads of buses and MPSoCs connected by means of general-purpose communication architectures. However, the development of application-specific NoCs for MPSoCs is a complex engineering process that involves the definition of suitable protocols and topologies of switches, and which demands adequate design flows to minimize design time and effort. In fact, the development of suitable high-level design and synthesis tools for NoC-based interconnects is a key element to benefit from NoC-based interconnects design in nanometer-scale CMOS technologies. This paper presents the design and implementation of FPGA based Network on chip (NoC) which is scalable packet switched architecture with advanced Networking functionalities such as store & forward transmission, error management, power management and security. All these features are built on basic NI core, which includes data packetization/depacketisation, frequency conversion, data size conversion and conversion of protocols with limited circuit complexity and cost.

Since 2001, there have been a myriad of papers on systematic analysis of multi-processor system on chip (MPSoC) and network on chip (NoC). Nevertheless, we only have a few of their practical application. Till now, main interest of researchers has been to adapt NoC to the communication intensive multimedia system like H.263. However, this paper attempts to expand the domain of NoC platform to one of the wireless security algorithms (TKIP), because its inter-component transaction pattern shows considerable characteristic for NoC. This paper consists of the explanation on operational sequence of the algorithm in chosen architecture and the brief illustration of important composing NoC blocks (Network Interface, Router).

In the near future, multi-processor systems-on-chip (MPSoC) will become the main thrust driving the evolution of integrated circuits. MPSoCs introduce new challenges, mainly due to growing communication through their interconnect structure. Current electrical interconnects face hard challenges to overcome such data flows. Integrated optical interconnect is a potential technological improvement to reduce these problems. The main contributions of this paper are: i) the optical network integration in a system-level MPSoC platform; and ii) the quantitative evaluation of optical interconnect for MPSoC design using a multimedia application

This paper presents methods for automatic generation of models of Transducer, a highly flexible communication module for interfacing Multiprocessor System-on-Chip (MPSoC) components. We describe the transducer architecture, comprising the bus interface, high-level communication controllers and buffer management blocks. The well-defined architecture of the transducer enables automatic generation of its Transaction-level and Register-transfer level (RTL) models. Moreover, the simple interface of the transducer provides for a well-defined software interface, making it easy to update the software after changes in MPSoC platform. Our experimental results show that MPSoC design for industrial-size applications, such as MP3 decoder and JPEG encoder, greatly benefits from automatic generation of transducer models. We found productivity gains of 9-23× due to significant savings in modeling effort. On the quality axis, we show that MPSoC communication design using automatically generated transducers has very little overhead in communication delay over a fully connected point-to-point communication architecture. Finally, we show that our automatically generated TLMs greatly reduce the system-level modeling time and provide a fast executable model for early functional validation.

Multi-Processors System-on-Chip (MPSoCs) have emerged as the enabler technology for new computational paradigms such as Internet-of-Things (IoT) and Machine Learning. Network-on-Chip (NoC) communication paradigm has been adopted in several commercial MPSoCs as an effective solution for mitigating the communication bottleneck. The widespread deployment of such MPSoCs and their utilization in critical and sensitive applications, turns security a key requirement. However, the integration of security into MPSoCs is challenging. The growing complexity and high hyper-connectivity to external networks expose MPSoC to Malware infection and code injection attacks. Isolation of tasks to manage the ever-changing and strict mixed-criticality MPSoC operation is mandatory. Hardware-based firewalls are an effective protection technique to mitigate attacks to MPSoCs. However, the fast reconfiguration of these firewalls impose a huge performance degradation, prohibitive for critical applications. To this end, this paper proposes a lightweight broadcasting mechanism for firewall reconfiguration in NoC-based MPSoC. Our solution supports efficient and secure creation of dynamic security zones in the MPSoC through the communication management while avoiding deadlocks. Results show that our approach decreases the security reconfiguration process by a factor of 7.5 on average when compared to the state of the art approaches, while imposing negligible area overhead.

This paper presents a virtual platform for the development and test of application software, low-level software, and hardware components for an MPSoC (Multiprocessor System-on-Chip) platform, where components are interconnected by a network-on-chip (NoC). The environment is aimed at the development of multithread real-time embedded applications in Java language. Communication and task management services are provided that are able to deal with real-time restrictions, following the RTSJ standard. SystemC models are used to describe processors and network connections that have equivalent descriptions in VHDL. Performance and power / energy evaluation are made possible, helping to shorten cycles for embedded system development, integration, and test.

The design of a Multiprocessor System-on-Chip (MPSoC) is a complex task, including steps as application development, platform configuration, code generation, task mapping onto the platform and debugging. An integrated environment covering most of these steps is a gap in the literature. The present work first details an MPSoC architecture, which supports the execution of distributed applications, including an operating system enabling multitask execution at each processing element. The MPSoC is heterogeneous, due to the support to different processor architectures. Then, a framework able to cover the design steps previously mentioned is presented. The framework enables the design space exploration for applications to be executed in the MPSoC, varying for example the number and type of processors, the memory size, the task mapping. Results demonstrate the correct operation for different MPSoC configurations, generated from the proposed framework. Such open-source framework enables the research community to investigate new subjects related to MPSoC and Network on Chip (NoC) design, as well as evaluate distributed applications in a multiprocessor environment.

Compensation of RF impairment in multi-band receiver based on RF sub-sampling

To quantitatively measure quality of service (QoS) in Network on Chip (NoC), several related aspects of the network service are often considered, such as end to end delay (EED), Throughput (Thp), Packet loss rate (PLR), etc. However, until now, no standard method of performance measurement and fewer techniques have been used to provide its definition. In fact, few papers have developed different methods to modelize QoS in NoC and provided an efficient and flexible way to monitor QoS. The originality of our approach is based on a proposition of a QoS–intellectual property module in NoC architecture to improve network performances. We implement an approach of QoS metrics modeling for NoC, using Analytic Hierarchy Process (AHP) on multi-parameter and multi-application for 4×4 mesh NoC environment. The results have shown that our QoS modeling approach is proven successful in providing a quantifiable representation. Therefore, QoS arbiter module interacts with other routers, the link utilization is balanced and network performance improved.

Over the years, system on chip (SoC) designs have evolved extensively sophisticated in order to fulfil the need of increasing complexity of running applications driven by the advancement of VLSI technology. The next generation multiprocessor system on chip (MPSoC) integrates hundreds of processing elements on a single chip, expected to achieve high performance, low latency, and low-power consumption. Tiled chip multicore processors (TCMP) with network on chip (NoC) have become a foundation for the computation critical embedded and real-time systems. Faster time-to-market restraint and business competition compelled manufacturers to look for the prospects of manufacturing SoCs integrated with various third party intellectual property (3PIP). Usage of 3PIP gave rise to exploit the underlying interconnect while adding some unwanted malicious circuit known as hardware trojan (HT), making NoC vulnerable to get attacked. A tiniest manipulation of any communication attribute by HT can degrade the overall behaviour of the system significantly while impacting NoC performance metrics. In this paper, we present one of such study considering HT malign behaviour of manipulating the output port of each incoming flit from specific ports once genuine route computation takes place and re-directs all to one port causing disruption in tile communication.The proposed HT is intermittent in nature and activates for few cycles. We study the behaviour of proposed confluence attack and analyze its impact over network level. The empirical evaluation exhibits the misbehaviour of the packet communication in terms of wrong usage of VCs and extra hop distance overhead. To validate the proposed work, various performance metrics like buffer utilization, virtual channel utilization, number of flits processed, link utilization, and the like are analyzed. We also show that such HTs are difficult to detect due to marginal increase at malicious port traffic leaving no trace of malicious conduct.