A simplified 24-step inverter without output transformers

PurposeMaintaining a balanced neutral point, reducing power loss, execution time are important criteria for the controlling of neutral point clamped (NPC) inverter. However, it is tough to meet all the challenges and also supplying the load current within the harmonic limit. This paper aims to maintain load current quality within the Institute of Electrical and Electronics Engineers 519 standard and meet the above-mentioned challenges.Design/methodology/approachThe output load current of a three-level simplified neutral point clamped (3 L-SNPC) inverter is controlled in this paper using model predictive control (MPC). The 3 L-SNPC inverters is considered because fewer semiconductor devices are used in this topology; this will enhance the reliability of the system. MPC is used as a controller because it can handle the direct current-link capacitors’ voltage balancing problem in a very intuitive way. The proposed 3 L-SNPC yields similar current total harmonic distortion (THD), transient and steady-state responses, voltage stress and over current protection capability as the conventional NPC inverter. To reduce the computational burden of the proposed SNPC system, two simplified MPC strategies are proposed, namely, single voltage vector prediction-based MPC and selective voltage vector prediction-based MPC.FindingsThe system shows a current THD of 2.33% at 8.96 kHz. The overall loss of the system is reduced significantly to be useful in medium power applications. The required execution times for the simplified MPC strategies are tested on the hardware dSPACE 1104 platform. It is found that the single voltage vector prediction-based MPC and the selective voltage vector prediction-based MPC are computationally efficient by 8.28% and 62.9%, respectively, in comparison with the conventional MPC-based conventional NPC system.Originality/valueMultiple system constraints are considered throughout the paper and also compare the SNPC to the conventional NPC inverter. Proper current tracking, over-current protection, overall power loss reduction especially switching loss and maintaining capacitor voltages balance at a neutral point are achieved. The improvement of execution time has also been verified and calculated using hardware-in-loop of the dSPACE DS1104 platform.

A new method for reducing the harmonics involved in the output voltages of a double-connected inverter is proposed. By adding four auxiliary switching devices and an interphase transformer with a secondary winding to the conventional 12-step inverter, output voltages of the proposed circuit can produce almost the same waveforms as a conventional 36-step inverter. In this paper, circuit performances and output voltage waveforms are discussed, and optimum parameters are derived. The effects on harmonic reductions are then clarified by theoretical and experimental results, and the ratings of system components are investigated. >

Multi-level inverter used in applications that require high power. The important factor in multi-level inverter is Total Harmonic Distortion (THD). This study discuss nine level cascaded H-bridge multilevel inverter. Also, proposed the effects of using filter on waveform and Total Harmonic Distortion (THD) of output voltage and current. Discussed LC low pass filter and sinusoidal pulse width modulation as control technique of switches. Comparison THD of nine level cascaded H-bridge multilevel inverter with and without filter. The proposed level and filter are design and simulate by MATLAB 2010 Version 7.11.0. The simulation results show the effects of using filter on THD and waveform of output voltage and current. Different methods for choosing filter value are used to illustrate the filter effect.

The diode clamped multilevel inverter (DCMLI) is an attractive high voltage multilevel inverter due to its robustness. The main draw back of the DCMLI is dc link capacitor voltage imbalance. A diode clamped inverter has been used in this research. The method used to balance the dc link capacitors is based on auxiliary switch-mode circuits, which are operated in a discontinuous inductor current mode. This research is focused on how to use auxiliary SMPS circuits to start up, balance, and shutdown the inverter. These functions are an issue in high voltage applications of the multilevel inverter. Simulation and experimental results are presented for the proposed auxiliary circuits operational technique.

Multilevel converters are very popular in medium/high power conversions due to their capability to generate high quality voltage magnitudes with low harmonics while employing devices of smaller voltage ratings. The output voltage waveform of multilevel inverter consists of multiple steppes of smaller magnitudes designed to reduce electromagnetic interference (EMI) commonly produced by rapid switching that generate lesser common mode currents at motor shaft and bearings due to reduced dv dt . The neutral point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) converters are considered as the three classical multilevel converter topologies which have found their way to industrial applications almost two decades ago. To expand the application field of multilevel converters by overcoming the challenges associated with classical topologies, new multilevel topologies and modulation techniques are developed. In this thesis, various NPC multilevel inverter topologies and its modulation techniques are investigated. Diode-clamped multilevel inverter (DCMI) for more than three-level operation is less attractive due to dc-link capacitor voltage unbalancing issues and increased conduction loses caused by the commutation of (n-1) × (n-2) clamping diodes connected in series per-leg of an n-level diode clamped inverter. A converter topology with minimum number of series connected devices which balance the total voltage equally between the semiconductors and new multilevel modulation schemes, which on more number of levels, redundant voltage vectors and zero common mode voltage vectors available in higher level DCMI, can be used together to solve the above mentioned issues. In this thesis, the voltage unbalance issues and capacitor voltage balancing techniques in DCMI are studied in detail. An extensive analysis of two modulation techniques, level-shifted PWM (LS-PWM) and space vector modulation (SVM) are presented and a SVM based voltage balancing strategy for three-level and five-level diode clamped inverters are developed by utilizing redundant switching vectors without the need of any additional controls or auxiliary circuits. The proposed balancing strategy is tested on a five-level reduced device topology. Multiple-pole multilevel diode clamped inverter (M2DCI) which is derived from three-level DCMI topology and uses lesser number of clamping diodes compared to the classic five-level DCMI. The capacitor currents as well as dc-link intermediate branch currents are obtained from the switching function model of five-level M2DCI, which reduces the number of calculations at each sampling periods while implementing the voltage balancing strategy when compared to sector based methods. The stability limits of the proposed voltage balancing strategy for M2DCI based on load power factor angle and modulation indices have been obtained at various load conditions. The investigations shown here are modeled in Matlab/Simulink® and PSIM environment and verified using experimental results. It is found that to achieve capacitor voltage balancing, modulation index is restricted to about 60% of its maximum value when loads of high power factor i.e PF ≥ 0.8 is connected at the converter terminals. Hence the proposed reduced device topology with SVM technique, which self-balances the dc-link capacitors has been extended for reactive power control in a grid connected environment. Additionally, the application of five-level multiple-pole multilevel diode-clamped converter (M2DCC) as STATic synchronous COMpensator (STATCOM) is investigated with the proposed space vector modulation based balancing strategy. The proposed scheme maintains a balanced voltage across the dc-link capacitors and exchange reactive power at various load conditions. Further, the performance of STATCOM and controllers are investigated through modelling done in Matlab/Simulink® and PSIM environment. The proposed reduced device topology together with SVM based voltage balancing technique is expected to give good performance for reactive power applications by reducing the converter losses, size, weight and THD.

Output voltage, output current and line current waveforms in a symmetrically pulse width modulated (SPWM) ac chopper are analyzed for harmonic content, displacement factor, distortion factor, power factor and efficiency. The results are compared with those of phase controlled ac chopper circuit to assess the superiority of SPWM ac chopper. A novel SPWM ac chopper with minimum number of active components is presented. The circuit operation and the design considerations are discussed.

Single stage boost multilevel neutral point clamped (NPC) Z-Source inverter are becoming prominent for better power quality in low power and medium power applications. The conventional multilevel NPC Z-Source inverter uses two equal DC sources or a split DC source as well as two inductors, two capacitors and two diodes in the intermediate network. However, the source current is discontinuous in NPC Z-Source inverter (ZSI) which is not desirable in some of the applications like fuels cell, UPS system, hybrid electric vehicle etc. Though source current is continuous in multilevel quasi Z-source inverter (q-ZSI), but it uses more number of high power passive reactive elements (inductors and capacitors) which increases the system size, weight and cost. In this paper a three level voltage boost NPC inverter is proposed, which can boost the input DC voltage and give required three level AC output in a single stage. It uses less number of high power passive elements (one inductor and two capacitors), four diodes and two active switches in the intermediate network at the same time retains all the advantages of conventional three level NPC ZSI/q-ZSI. As a result, system size, weight and cost are reduced. Along with the above advantages, proposed inverter requires a single DC source and the source current is continuous in nature. The steady state mode of operation of the proposed inverter is discussed and voltage gain function is derived. The PWM technique for the inverter is also discussed. The simulation and experimental verification of the inverter has been done using MATLAB Simulink and laboratory prototype respectively.

Two and three level VSC inverters are the building blocks of most of inverter applications necessitating the employment of appropriate switching techniques that result in harmonic free sinusoidal output. The paper presents the generalized method for harmonic elimination in two and three level voltage sourced converter. The technique used for suppression of selective low-ordered harmonics form the inverter's output voltage waveform is Selective harmonic elimination (SHE). The inverter's output voltage waveform is mathematically modeled using Fourier series that results in the system of nonlinear equations. The non-linear equations are solved for eliminating the specific low order harmonics. The main objective in calculating appropriate switching angle is to minimize the value of Total Harmonic Distortion (THD). To solve the system of non-linear equations numerical method Newton Raphson is applied and appropriate switching angles are calculated. The remaining uneliminated higher order harmonics are eliminated by connecting appropriate value of filter at the output stage of VSC inverter. The model of two level VSC is simulated in SimPowerSystem Matlab tool bar together with the algorithm of Newton Raphson technique. The time domain plot and frequency spectrum of inverter's output waveform is presented in the results section. The results of two and three level VSC inverters are analyzed and debated together with the comparative analysis on the basis of THD. Moreover, a comparison is presented on the basis of IEEE standard Std. 519 and EN 50160.

In this research project, an AC Cûk voltage regulator has been proposed for maintaining constant voltage across the load during wide range of input voltage fluctuations. The proposed AC Ck voltage regulator made of practical IGBT switches has been investigated for both manual and automatic control circuit. A fraction of the output voltage is taken as the input voltage of the control circuit and produce the error signal if any changes occur in the output voltage. The modified error signal is used to make PWM signals for switching devices as per output voltage of regulator. The PWM controls the ON/OFF time (Duty cycle) of switching devices (IGBTs) of the proposed regulator. As a result the regulator is maintaining a constant voltage across the load during any change in supply voltage. The simulation waveforms and the calculated total harmonics distortion (THD) values are compared with previously studied AC Buck-Boost regulator. The observed simulated waveforms of output voltage, output current and input current and THD values have been improved in case of proposed AC Cûk voltage regulator.

The apparent advantages of Multilevel Inverter (MLI) topologies in handling medium and high power with less loss in switching and lower harmonic distortion in an output voltage waveform makes it better than the conventional inverter. However, the MLI topologies utilize a large number of DC power supplies and power semiconductor devices. They also have a higher value of total standing voltage (TSV). Moreover, capacitor voltage balancing problems, self-voltage boosting inability, and complex control techniques require a relook and improvement in their structure. More recently, Switched-Capacitor Multilevel Inverter (SCMLI) topologies have been proposed to overcome the shortcomings of MLIs. In this paper, a generalized structure for a single-phase switched capacitor multilevel inverter (SCMLI) with self-voltage boosting and self-voltage balancing capability is proposed. A detailed analysis of a general structure of SCMLI is presented. The comparative analysis of the structures is carried out with recently reported topologies to demonstrate superiority. An optimized low-frequency modulation controls the output voltage waveform. The simulation and experimental results are included in the paper for single-unit symmetric (9-level voltage) and asymmetric (17-level voltage) configurations.

For most medium voltage high power applications, Neutral Point Clamped (NPC) three-level inverter is a preferred choice due to its advantages such as low cost, light weight and compact size. Space vector modulation is widely used in real-time digital control for power converters. It is especially suitable for use in NPC multilevel inverters due to its good harmonic profile, flexibility and easy digital implementation. This thesis focuses on the space vector modulation for high power three-level NPC inverter, where the switching frequency of the semiconductor devices is nominally below 1 OOOHz to reduce the power loss of the switching devices. The conventional space vector modulation (SVM) scheme for the three-level NPC inverter produces even order harmonics in the output voltages, which are not desirable for most industrial applications. In this thesis, the mechanism of even order harmonic generation is analysed. A new space vector modulation scheme, which can eliminate all the even order harmonics, is proposed. The performance of the new design is investigated and simulation results are provided for the verification purpose. The harmonic and THD profiles are compared with those of the conventional SVM scheme. The elimination of even order harmonics is achieved at the expense of a slight increase in the switching frequency. The proposed space vector modulation scheme can be applied to other types of converters for the even order harmonic elimination. An algorithm is developed to mitigate the neutral point potential deviation, which is a common problem in the NPC inverters. The simulation results show that this algorithm is suitable for both conventional and the proposed space vector modulation schemes.

This research focuses on an independent photovoltaic power generation system with supercapacitor energy storage as the study subject. The model is simplified, and the photovoltaic power generation light emitting diode (LED) device is designed based on the given parameters. This system selects a Boost-type step-up converter for the supercapacitor charging circuit, capable of achieving Maximum Power Point Tracking (MPPT). The supercapacitor discharge circuit employs an LM2596 series regulator to power the rated load LED (12 V, 1 W), providing good linear regulation capability. In designing other hardware components of the device, the characteristics of a photoresistor are utilized to implement an automatic load switch circuit. An efficient single-chip integrated circuit LM2575 series is used as a regulator to convert the voltage across the supercapacitor terminals to +15 V and +5 V. Considering the need to collect the output voltage of the photovoltaic cell array and the voltage across the supercapacitor terminals, a resistor divider method is used to sample these two voltages. The sampling circuit includes a resistor divider circuit and a linear optocoupler isolation circuit. An HNC-25LTS series Hall current sensor is used for current sampling to measure AC, DC, and pulse signals under electrical isolation conditions. The supercapacitor, solar photovoltaic panel, control unit, and the main circuit for supercapacitor charging and discharging have been assembled in the experiment. Connecting the charging and discharging circuit with the photovoltaic panel and LED, the system provides power to the LED during the night. Under varying light intensity and temperature conditions, the photovoltaic output voltage waveform, PWM waveform, and Boost circuit output voltage waveform remain stable when reaching the MPPT point. The output power with added MPPT control at different times is compared. The results indicate that the designed system has effectively achieved the functionality of MPPT for solar energy.

This paper introduces a new asymmetrical multilevel inverter (MLI) for photovoltaic generation systems (PVGS). The proposed MLI utilizes a single dc source, PV array, and four series-connected capacitors to generate the nine-level output voltage at reduced number of switching devices. The proposed inverter is composed of the main and auxiliary circuits. The main circuit is a single-phase H-bridge inverter, which is responsible for the output voltage polarity. The auxiliary circuit is a special structure of switching devices to achieve the multilevel output voltage. Perturb and observe technique (PO an increased output voltage levels at a reduced switches number, single isolated dc supply is needed, low switching loss, low total harmonic distortion (THD), low dv/dt stress on the switches and hence, low switches ratings and cost. The grid-tied PVGS, which applies the MLI, is simulated using MATLAB/SIMULINK software. A real time validation of the PVGS has been carried out.

This study aims to present a two‐output three‐level series‐resonant inverter together with an implementation and experiments for an induction melting application. A three‐level circuit is applied for each branch of inverter in order to decrease the voltage stress on switching devices. A phase‐shifted pulse‐width modulation (PSPWM) with variable frequency control is applied for providing and maintaining a zero‐voltage switching condition over a wide load range. In addition, the PSPWM could provide symmetrical output voltage and current waveforms that result in decreasing the THD v and THD i of output waveforms and harmonic losses of high‐frequency transformer cores comparing to other PWM schemes. Finally, the prototype was designed, built, and tested to verify the consistency between the experimental results and theories of the proposed inverter.

A carrier-based synchronous type single phasephase synchronous inverter (S-PSI) is proposed to develop the inverter output phase and voltage waveform. The major problem of the microgrid connected inverter is unbalanced DC supply, high switching loss, power quality and phase error. Therefore, to overcome those issues, a phase synchronous technique can perception not only conventional DC to AC inverter but also low-frequency inverter source ripple current reduction with lower switches of the inverter. However, a carrier-based synchronous PWM control technique is proposed for capable of regulating both side of the inverter input and output performance. The working performance of the S-PSI is analyzed, including steady-state behavior, efficiency, and circuit parameters. As well, the equivalence of the switching control technique and the similarity of inverter evaluate circuit parameters are exposed between this S-PSI and a traditional two-level inverter. In addition, lowpass LCL filters are utilized to convert squire wave to sine wave with same frequency and to reduce the higher harmonic distortion of the microgrid voltage. Balanced resistive load of = 11 $\Omega$ for star configuration and input DC voltage, ± 340V have assume to design the inverter. From the simulated results, the carrier-based S-PSI systems are developed the phase error of 55%, reduced 11% of THD and the conversion efficiency of 97.02%. Finally, it highly appreciated that the proposed design will improve the microgrid system.