A SimPLR method for routability-driven placement

Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global floorplacement method that combines a hierarchical simulated annealing floorplanning method with a partitioning-based global placement technique. A novel area migration method, formulated as a min-cost, max-flow network flow problem, is used to improve area utilization, and provide a communication mechanism between the partitioning engine and the placement method for better design quality. The network flow area migration method can be used in managing incremental changes in the design as well. Our global placement wire length is 12% better than the detailed placement wire length of a previous work, while our global placement is almost 8 times faster than their global placement.

During physical synthesis, global placement and incremental optimization steps such as gate sizing, buffer insertion and timing-driven placement, produce placements where cells are overlapped or misaligned with respect to sites and rows predefined in the used standard cell library. Therefore, a legalization procedure must be used to keep the placement legality. In the case of incremental optimization techniques, the legalization step can be applied as a final step, after each optimization iteration or even after each primitive placement transformation. Although different legalization strategies are used by different works on incremental optimization techniques found in the literature, they do not present practical results on how those different strategies impact on the runtime and quality of the optimized placements. This work investigates such issue by comparing the runtime, timing degradation, density profile and wirelength resulted from using three legalization strategies on an incremental timing driven placement technique. Experimental results show that incremental legalization is from 22% to 71% faster than a single final legalization step and achieves similar density and wirelength profiles, but may increase timing violations up to 48% (9% on average). On the other hand, legalizing the circuit after each optimization iteration is the least interesting strategy, since it leads to similar quality results than a single final legalization, at the cost of a runtime about 3.2 times greater on average. Therefore, incremental legalization may be an interesting strategy for incremental optimization techniques due to its shorter runtime. Finally, we point out alternatives to improve the quality of incremental legalization techniques.

As the complexity and scale of FPGA circuits grows, resolving routing congestion becomes more important in FPGA placement. In this paper, we propose a routability-driven placement algorithm for large-scale heterogeneous FPGAs. Our proposed algorithm consists of (1) partitioning, (2) packing, (3) global placement with congestion estimation, (4) window-base legalization, and (5) routing resource-aware detailed placement. Experimental results show that our proposed approach can give routable placement results for all the benchmarks in the ISPD2016 contest and can achieve good result compared to the other wining teams of the ISPD2016 contest.

Agricultural mechanization impacts on agricultural productivity and society development far-reaching. The emergence of ASIC (Application Specific Integrated Circuit) provides possibility for full intelligence and automation of agricultural products. Placement is a key step in the physical design of ASIC. Legalization is core task of the detailed placement after global distribution of generous standard cells. It removes cells overlap, aligns them to the sites and places them to their final position. A congestion-length driven legalization algorithm with minimum total movement is presented in this paper. The algorithm takes the total wire-length and congestion as objective and considers the site constraint to legalize cells with minimum movement. It contains series of phases to place cells to their optimal site, like formation, Inter-Row cells distribution and Intra-Row cells overlap elimination. But at the same time, it keeps global placement result and optimizes total wire-length at most. On the ISPD 2011 and DAC 2012 Contest Benchmark Suite, with the official valuation protocol, the routability-driven legalization algorithm outperforms original wirelength-driven algorithm almost every contestant.

It is presented an analytic non-linear method for global placement of cells in circuits based on Dynamic Systems Theory, also known as Chaotic Systems. The related developed tool is called Chaotic Place. The two-dimensional structure of the cells of a circuit was obtained by the reconstruction of a Strange Attractor (Takens' Theorem). The experiment was tested in FPGAs using the “FPGA Place-and-Route Challenge” benchmarks. For comparison of results, the Half-Perimeter-Wire-Length (HPWL) was used as a metric and focus. The experiment results show a 6% reduction in wirelength, in average, when compared to the state-of-the-art placement tools for homogeneous FPGAs.

Wirelength is a traditional optimization objective in global placement algorithms. To eliminate cell overlaps, spreading forces need to be added to pull cells away from highly congested areas. At the same time, to optimize wirelength, the quadratic nature should be maintained. In this paper, several techniques are proposed to optimize spreading force orientation and modulation. Specifically, a percentage-driven method is proposed to cluster overfilled bins, followed by a center-uniformization algorithm to demarcate the expand region for the cluster. Finally, cells are distributed evenly within each expand region while maintaining relative cell positions and minimizing cell displacements. Experimental results show that the global placer that integrated with the proposed strategies achieves 13.0% and 2.1% less wirelength compared with Capo10.5 and Aplace3, respectively.

A modern FPGA often contains an ASIC-like clocking architecture which is crucial to achieve better skew and performance. Existing conventional FPGA placement algorithms seldom consider clocking resources, and thus may lead to clock routing failures. To address the special FPGA clocking architecture, this paper presents a novel clock-aware placement algorithm for large-scale heterogeneous FPGAs. Our algorithm consists of three major stages: (1) a nonlinear global placement framework with clock fence region construction, (2) a clock-aware packing scheme, and (3) clock-aware legalization and detailed placement. We evaluate our results based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite. Compared with the top three winners, the results show that our algorithm achieves the best overall routed wirelength. On average, our algorithm outperforms the top-3 winners by 3.6%, 7.5%, and 12.9% in routed wirelength, respectively.

The NP-hard Rectilinear Steiner Minimum Tree (RSMT) problem has been studied in the VLSI physical design literature for well over three decades. Fast estimators of RSMT cost (which reflects routed wirelength) are a required ingredient of modern physical planning and global placement methods. Constructive estimators build heuristic RSMTs whose costs are used as wirelength estimates; notably, these include FLUTE[8]. Analytic and lookup table-based estimators include the methods of Cheng[7] and Caldwell et al. [3]; the latter is based on both the number of points and the aspect ratio of the pointset in the RSMT instance. We observe that the physical design literature has numerous evaluations of RSMT heuristics and estimators on random pointsets, and that the relative merits of heuristics and estimators have been determined based on this use of random pointsets. In this paper, we show that a pointset attribute which we call L-ness highlights the difference between real placements and random placements of net pins. We explain why placements of netlists in practice result in pointsets with much higher L-ness than random pointsets, and we confirm this difference empirically for both academic and commercial placement tools. We further present an improved lookup table-based RSMT cost estimator that includes an L-ness parameter. Last, we illustrate how differences between Steiner tree heuristics can change depending on whether real or random pointsets are used in the evaluation.

Routing is a critical and time-consuming step in modern VLSI design flows, where the quality of the global routing algorithm directly impacts both routing time and the final design quality. Efficient global routers are essential for optimizing design performance while reducing overall routing time. The innovation lies in the extension and optimization of the routing Directed Acyclic Graph (DAG) forest to represent the 2D routing space for all nets, enabling coordinated selection of Steiner trees, 2-pin routing paths, and efficient handling of congested areas. To perform topological analysis within the DAG forest, The DAG employ DAG-GNN, which utilizes continuous optimization methods to mitigate congestion, with acceleration provided by deep learning toolkits on GPUs. The experimental results on the ISPD contest benchmarks show that compared to the DGR, the algorithm concurrently reducing total wirelengths from 2.45% to 5.69% and via numbers from 2.2% to 3.5% in congested testcases.

Recent work has established Lagrangian relaxation (LR) based gate sizing as state-of-the-art providing the best power reduction with low run time. Gate sizing has limited potential to reduce the power when the timing constraints are tight. By adjusting the arrival times of clock signals (clock skew scheduling), the timing constraints can be relaxed facilitating more power reduction.Previous LR attempts at simultaneous gate sizing and skew scheduling solved a minimum-cost network flow problem for updating the Lagrange multipliers in each LR iteration, and for optimality assumed continuous sizes with convex delay models. We propose an alternative approach, modifying a LR discrete gate sizing formulation with table lookup non-convex delay models, which are more accurate for modern process technologies. For the Lagrange multiplier update, we use a projection heuristic that is much faster than solving the minimum cost network flow problem.On the ISPD 2012 gate sizing contest benchmark suite, our proposed approach outperforms the previous min-cost flow based approach by saving 5.3% more power and is 70x faster. Compared to sizing alone with the state-of-the-art LR gate sizer, skew scheduling with sizing saves 19.7% more power with a small runtime penalty.