A simulation tool development roadmap to support a scalable silicon photonics design ecosystem

Coupling Of Synthesis And Layout: Challenges And Solutions

In this paper, CASCADE, a standard supercell-based design methodology, its supporting automated design flow, and associated design tools, are presented for 3D implementations of a class of interconnect-heavy application-specific very large-scale integrated circuits. In CASCADE, a system is first partitioned and synthesized using standard 2D design tools to a set of supercells with the same height and varying widths. With this, the 3D design is reduced to 3D supercell placement and 3D-via assignment. A congestion-driven simulated-annealing method is used to find a 3D placement of supercells to minimize the total wire length, the longest wire length, and the number of 3D vias and routing density. To efficiently estimate the routing density of a 3D grid space within the optimization loop, a simple probabilistic congestion model with an incremental congestion computation has been developed. Once the supercell placement is fixed, the problem of assigning 3D vias to accomplish minimal 2D routing densities and uniform 3D-via distribution is solved by an efficient min-cost-max-flow method. The proposed methods have been implemented and tested on a set of ISPD98 circuit benchmarks. Experimental results have shown that the proposed congestion-driven 3D supercell placement and flow-based 3D-via-assignment tools have yielded satisfactory placement with small-area, low-congestion, short-wire-length, few, and uniformly distributed 3D vias. Furthermore, an excellent correlation between routing-density estimation by our model and the actual routing performed by a commercial router has been observed. We have applied the proposed 3D design methodology, tools, and flows to tape out an over 4-million-gate low-density parity-check decoder in a three-tier 0.18- fully depleted silicon-on-insulator 3D CMOS process manufactured by MIT Lincoln Laboratory. The postlayout simulation of this DRC-clean layout design showed an about ten times improvement on the power-delay-area product compared to a 2D implementation in the same process.

The need to improve the energy efficiency of buildings requires new and more efficient ventilation systems. It has been demonstrated that innovative operating concepts that make use of natural ventilation seem to be more appreciated by occupants. This kind of system frequently integrates traditional mechanical ventilation components with natural ventilation devices, such as motorized windows and louvers. Among the various ventilation strategies that are currently available, buoyancy driven single-sided natural ventilation has proved to be very effective and can provide high air change rates for temperature and IAQ control. However, in order to promote a wider applications of these systems, an improvement in the knowledge of their working principles and the availability of new design and simulation tools is necessary. In this context, the paper analyses and presents the results of a research that was aimed at developing and validating numerical models for the analysis of buoyancy driven single-sided natural ventilation systems. Once validated, these models can be used to optimize control strategies in order to achieve satisfactory indoor comfort conditions and IAQ. Practical Implications Numerical and experimental analyses have proved that short-term airing by intermittent ventilation is an effective measure to satisfactorily control IAQ. Different control strategies have been investigated to optimize the capabilities of the systems. The proposed zonal model has provided good performances and could be adopted as a design tool, while CFD simulations can be profitably used for detailed studies of the pollutant concentration distribution in a room and to address local discomfort problems.

Despite their long-time existence and significant capabilities, computational modeling, simulation, and design tools have been underutilized for textiles in general, specifically limiting the ability of knitted textiles to be widely deployed and to reach their full industrial potential in advanced functional fabrics and garments. These computational tools require a robust representation and efficient evaluation of the spatial, material, and physical properties of textile structures. An example of an efficient modeling method for knitted fabrics is TopoKnit, a process-oriented representation for capturing the topology of weft-knitted textiles. In this paper, we extend TopoKnit and present new algorithms that may be used to determine additional topological structures and assess the structural integrity and stability of knitted textiles modeled by this fundamental data structure. We compare our results with outputs from a commercial software system to confirm the effectiveness and validity of our algorithms. These new capabilities provide a foundation for open technologies that can accurately model and predict the geometric and mechanical properties/behaviors of knitted textiles. They will support the development of computational design and analysis tools that will obviate the expensive and wasteful trial-and-error process of knitting and testing actual fabrics in the preproduction phase of textile manufacturing.

Specific congestion control mechanisms for wireless vehicular communications have been studied extensively in previous research. Various mechanisms with important functionality for a scalable vehicular communications system design have been identified, and their applicability for certain communications scenarios has been studied in the past. Definition of overall resource utilization principles for guiding functional specification and complementary design of congestion control tools has been a missing aspect of previous research. This paper proposes a suitable scalability principle for each major vehicular communication scenario: periodic safety broadcasts, event-driven safety broadcasts, and unicast message forwarding. Each scenario section investigates an appropriate design of individual congestion control tools for the implementation of related scalability principle. It is then described how individual tools shall complement one another.

This paper focuses on the development of trusted tools for designing digital circuits in the basis of heterogeneous field programmable gate arrays (FPGAs). Designing heterogeneous FPGAs is one of the most actively growing areas in Russian microelectronics at present. The paper discusses the main problems and challenges associated with the development of trusted computer-aided design tools. The authors propose a relevant approach to the development of a computer-aided design system based on the use of open-source software tools together with proprietary developments for its critical components. This approach allows to increase the efficiency and reliability of the design process in the basis of heterogeneous FPGAs. The paper considers such stages of the design flow in the basis of heterogeneous FPGAs as logic synthesis and technology mapping, different stages of layout synthesis and static timing analysis. The work is of interest to specialists in the field of microelectronics, as well as to researchers involved in the development of IC design tools and systems. The research results contribute to the improvement of existing IC design methods and tools, as well as to the development and expansion of the Russian electronic component base.

The current boom in WDM optical networks has created a huge demand for a variety of optical components. Due to their compactness, robustness and suitability to large scale production Photonic Integrated Circuits (PIC's), that combine a number of optical elements on a single chip, will play an important role in satisfying this demand. In PIC's the light is routed through certain paths using total internal reflection at waveguide interfaces. Optical Design Automation tools (ODA) play a paramount role in reducing the development time of these PIC's. In this paper we will present an overview of the most commonly used design tools as well as their requirements to allow for a short and efficient design cycle.

A reduction of development costs will have a significant impact on the total cost of the vacuum electron devices. Experimental testing cycles can be reduced or eliminated through the use of simulation‐based design methodology, thereby reducing the time and cost of development. Moreover, by use of modern optimization tools for automating the process of seeking specific solution parameters and for studying dependencies of performance on parameters, new performance capabilities can be achieved, without resorting to expensive cycles of hardware fabrication and testing. Simulation‐based‐design will also provide the basis for sensitivity studies for determining the manufacturing tolerances associated with a particular design. Since material properties can have a critical effect on the performance of the vacuum electron devices, the design tools require precise knowledge of material characteristics, such as dielectric properties of the support rods, loss profile etc. Sensitivity studies must therefore include the effects of materials properties variation on device performance. This will provide insight for choosing the proper technological processes in order to achieve these tolerances, which is of great importance for achieving cost reduction. A successful design methodology depends on the development of accurate and efficient design tools with predictive capabilities. These design tools must be based on realistic models capable of high fidelity representation of geometry and materials, they must have optimization capabilities, and they must be easy to use.

This paper presents an approach towards substation automation integration tools design. In the light of recent standardization, namely IEC 61850, object-oriented information modelling will play an important role in the design of automation systems in the near future. Substation automation, as well as other utility automation domains, requires specific design engineering tools to cope with increasingly demanding budget, resource and time requirements in an engineering domain where information complexity and size are growing. The shift towards object-orientation and model-driven design will facilitate the design of automation systems and will require handling of domain, system and device models in an integrated computer-aided engineering environment. A core architecture based on the OMG meta-modelling framework is proposed, in order to establish a flexible and scalable integrated design environment. This proposal is the outcome of a preliminary study on the implementation of system engineering tools. This paper introduces the application domain, describes the requirements for a tool environment and proposes a meta-modelling architecture as a tool design guideline.

Topology modeling is a challenging topic in the design and development of tools that simulate the behavior of interconnection networks. During the last years we have seen the birth of several simulation tools and frameworks modeling interconnects, some of them doing brilliant efforts to do the code re-usable and extensible. The main differences among these simulation tools and frameworks is the level of granularity and abstraction of their network models. Different network models may generate duplicated efforts in modeling certain aspects of them, such as the network topology or the routing algorithm. If the topology generation and routing algorithm modeling were separated from the modeling of other network aspects, then the simulator developers could focus on developing non-existing models and new functionality, without wasting time in doing a work previously done by other simulation tool developers. In this paper we describe TopGen, an external library that can be integrated with any tool that simulates interconnection networks. TopGen provides a compendious of well-known network topologies that can be used to interconnect the network components, such as end nodes, channels, switches and routers. It also provides the corresponding knowledge to apply a compendious of routing algorithms to the modeled network topologies. TopGen also supports the definition of customized topologies that are not the standard ones, thanks to a special interface used for this purpose. We also provide details on how to integrate TopGen with a network simulator, by means of a simple API. Finally, we describe several use cases of the TopGen library.

There are available commercial and education network analysis, design, simulation and discovery tools in the market. They help the users/designers in many aspect but different tools are developed for different purposes. Thus, very often such tools are addressing different issues in the network design process, which are complementary to each other. Therefore, these tools can be used in a manner of complementing to each other to cover all aspects of user requirement and because of that there is a genuine need to integrate such tools. This paper is dedicated to the problem of integrating such independently developed network planning, network design and network simulation tools. It is looking at the problem of network meta description language as well as at principles of defining such language using current experience of various tools. Examples of the meta language definitions are shown as well as principles of building a software for conversion between different network models are illustrated.

Efficient photonic circuit simulation tools are essential for the design and optimization of photonic integrated circuits (PICs). However, the computational speed of current commercial simulators remains insufficient to support large-scale circuit optimization and statistical verification. In this paper, a multimode scattering matrix computation method based on a multimode subnetwork growth approach (referred to as MSG) for efficiently calculating the frequency-domain response of photonic circuits is proposed. The presented method starts with accurate photonic devices modeling leveraging the multimode scattering matrix. It then utilizes the established multimodal models to precisely characterize component parameters and topology information of the arbitrarily interconnected multiport photonic circuit. By employing an iterative strategy that connects only two subnetworks at each step, the global response is progressively computed, which significantly reduces the complexity of matrix inversion. The sequence of network connections is optimized using a suboptimal ordering algorithm, further minimizing the total computational cost. Benchmark results demonstrate that our approach enables fast multimode simulation, delivering over twice the speed of commercial simulators and strong engineering applicability.

Planar Photonic Circuits can perform many useful functions in optical communications systems, such as wavelength division multilplexing (WDM), optical channel add/drop, fibre/waveguide coupling, and amplifier gain equalization. They perform these functions by the interaction of the device structure with the light inside them. There are very effective and proven numerical methods available for modelling this interaction, such as the Beam Propagation Method (BPM), the Finite Difference Time Domain (FDTD) method, and coupled mode theory (CMT). However, these methods work on a microscopic level (typically the smallest distance is about 0.1 microns), but photonic circuits, on the other hand, can occupy an entire wafer (scale: 10 cm). The analysis must span 5 or more orders of magnitude in the change in scale. The successful analysis needs to combine the basic microscopic techniques with an approach at a more abstract, or system, level. It is interesting that software designed for the analysis of optical communication systems can be applied to planar photonic circuits. This paper shows an example of a practical photonic circuit, a lattice filter, that cannot be analysed by BPM alone. It will be demonstrated that when used with a system level analysis, the whole device can be simulated.

In this paper the specialized processors, their design flow and application in computer and cyber-physical systems were described. Reconfigurability in computer and cyber-physical systems design was considered. The Chameleon©C2HDL design tool that is intended for the specialized processors HDL-model automatic generation from the algorithm described in the ANSI C language was considered and evaluated. Based on this design tool, cloud design and production as a service tools were proposed. New methods for computing organization in reconfigurable computer and cyber-physical systems by giving for them the possibility of self-configuration due to the using of specialized processor automatic design tools were proposed.

The very large development of home and domestic electronic appliances as well as portable device has led the microelectronics industry to evolve in two complimentary directions : “More Moore” with the continuous race towards extremely small dimensions hence the development of SoCs (System on Chip) and more recently a new direction that we could name “More than Moore” with the integration of devices that were laying outside the chips and here the creation of SiPs (System in Package).These two approaches are not in competition one with the other: the paper will show some examples of integrated nano systems that use several SoCs.The technology we have developed is called Silicon Based System in Package. The first products using this technology are now in volume production and used mainly in the field of wireless communications.This new technology relies on four pillars. Passive integration is the first. Very efficient and high quality factor capacitors and inductors have been integrated, allowing the creation of complete modules including active devices, filters and decoupling capacitors. High-density MOS capacitors with 1-1000 nF capacitance, and as high values as 25-250+ nF/mm2 specific capacitance have been fabricated in macroporous Si-wafers, containing over 1 billion macropores. Typically an ESR less than 100 mÙ and an ESL less than 25 pH were found for capacitors over 10 nF. This novel concept is an important step forward in improving the stability of power-amplifier modules by replacing conventional SMD technology.Whereas generations with capacitors density of up to 100 nF/mm2 will be using “conventional” materials and structures, the next steps in the roadmap will call for new 3D structures and materials such as high-k dielectric.The second element is advanced packaging. New technologies, such as the assembly of Silicon chips onto other Silicon chips, also named “double flip chip” have been developed. This has been made possible thanks to the combination of the most advanced microbumping and die placement techniques. In addition to a tremendous reduction of size (up to a factor of 10 to 20) these techniques have also brought a better repeatability of system performance.The third element has been the development of design tools that allow a seamless system design for engineers used to IC design tools and flows. Our Design Environment allows co design of multiple technologies chips and their integration in a single system. This IC-like Design Environment has contributed a lot to the adoption of the technology.Testing is the fourth element and is one of the economical enablers of the technology. The key words are: “known good die”, RF test, system test, etc. Some innovative RF probing and full on wafer subsystem test will be shown. Even though efficient test is not vital for the technical feasibility of this system integration, it becomes very quickly one of the most important enablers, especially when we deal with very high volumes of production. The conclusion of the paper will be an open door to the future. Some innovations like the integration of light or even energy storage inside our SiPs will be presented.