A Spice Behavioral Model of Tunnel Diode: Simulation and Application

A PLL behavioral model for a single event caused by a radiation strike is proposed in this paper. This model describes the behaviors of the radiation-induced transients in the circuit blocks of the PLL. The simulation results when comparing our proposed model with a SPICE simulation showed that our proposed model is identical to that of SPICE, but our proposed model is about 2,500 times faster. Our behavioral model is used to investigate the minimization strategy of the recovery time from the single event. We found after conducting a large number of simulations that a system with a damping factor of around 1 is the optimal design for a given recovery time. We were able to reach this conclusion within a short period of time thanks to the high-speed behavioral simulation.

The paper presents a complete simulation model for a graphene-based micro-Hall sensor that contains the functional model, as well as the temperature and noise influences, starting from the experimental characteristics described by Xu et al. in [1]. The mathematical expressions obtained from fitting the sensor characteristics are used as input data in the SPICE model. This model was implemented in PSpice with the help of ABM (Analog Behavioral Modeling) blocks. Once the model is validated, it can be successfully adopted and applied to describe the behavior of the other linear magnetic sensors.

The basic behavior of a tunnel diode when it is used as an optoelectronic device is presented. It is shown that a tunnel diode can be used as an electro-optic modulator, as a device that exhibits self-induced transparency, or as a wavelength converter (for both upconversion and downconversion). The tunnel diode has optical bistability even if it is not placed inside a Fabry-Perot resonator. Numerical estimations are made for some of the parameters of interest for an optoelectronic device and are compared with those of other existing semiconductor-based optoelectronic devices. As the numerical estimates show, a tunnel diode can be a highly efficient optoelectronic device with an extremely wide area of application.

Chapter 8 - Convergence Problems and Error Messages

In Very Large-Scale Integration (VLSI) design, minimizing area and optimizing device performance have become paramount as traditional MOSFET scaling approaches fundamental limits. Energy efficiency is now a primary goal due to MOSFET scaling challenges. Multi-valued logic (MVL), such as quaternary (2-bit) logic, offers a potential solution by increasing information density and reducing interconnect complexity. However, implementing four discrete voltage levels in quaternary logic requires novel device technologies. This work explores Spatial Wavefunction Switched FET (SWS-FET) devices – quantum well transistors enabling multi-state carrier transport – as a size- and power-efficient platform for quaternary logic. We present the development of complementary n-channel and p-channel SWS-FETs to encode the four logic states (00, 01, 10, 11). The proposed SWS-FET quaternary logic gate circuits are designed and simulated using an 180nm CMOS-compatible device model. The accuracy of the SWS-FET circuits is verified in Cadence Virtuoso using a combination of the industry-standard BSIM transistor model and an analog behavioral model (ABM) to capture multi-threshold behavior. Circuit simulations of the 2-bit NOR gate demonstrate that using SWS-FETs reduces transistor count by approximately 42% compared to an equivalent CMOS implementation and by up to 68% compared to current-mode MVL designs. These gains are achieved with low power dissipation and competitive switching speeds, highlighting the promise of SWS-FET technology for energy-efficient multi-valued logic design.

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

When calculating the belief reliability of electronic products, it is often used to establish a circuit simulation model to perform Monte Carlo analysis to obtain the key performance degradation parameters of the product. In this process, the lack of electronic component models is often a major difficulty that restricts this method. This article introduces the analog behavioral model (ABM) modeling method of electronic products, and gives the modeling process for power converters and relays, and substitutes the established model into a certain type of control circuit for transient simulation. Verity the usability of the model. Then use Monte Carlo simulation in circuit simulation to obtain key performance simulation results in the circuit. Finally, the belief reliability of the control circuit is calculated based on the principles of the four equations for the reliability.

An oscillator with a series connection of tunneling diodes produces significantly higher power than a single diode oscillator. However, a circuit with series-connected tunneling diodes biased simultaneously in the negative differential resistance (NDR) region of the I-V curve is dc unstable. This dc instability makes the series connection oscillator fundamentally different from a single diode oscillator. Associated with the dc instability are the phenomena of minimum oscillation amplitude and frequency. Due to the minimum oscillation amplitude, it is critical to provide the impedance match between the oscillator circuit and the series connection at the desired oscillation amplitude level. An in depth, comprehensive analysis of the dc instability is given here. Based on this analysis, a numerical procedure is developed to accurately predict the minimum oscillation amplitude and frequency. Time domain simulations which give further insight into series-connection oscillator behavior are discussed. The effect of increasing the number of diodes on the oscillator performance is explored as well. Based on numerical and simulation results, oscillators with several tunnel diodes connected in series were designed and tested. Experimental results that confirm the existence of the minimum oscillation amplitude are presented for oscillators with two, three, and four tunnel diodes.

In this paper, the static and dynamic characteristics of a 1200 V and 120 A silicon carbide (SiC) MOSFET power module has been measured, simulated and verified in the PSpice circuit simulation platform. Experimental measurements and PSpice simulations are performed to extract the technology dependent modeling parameters. The model is implemented in the PSpice circuit simulation platform using both standard components and analog behavior modeling (ABM) blocks. The simulation results of the model is fairly accurate and correlates well with the measured results over a wide temperature range. The developed model is used to facilitate converter design at cell level and hence predict and optimize the cell performance (i.e., energy losses) with varying circuit parameters (e.g., stray inductances, temperatures, gate resistances etc.,).

An analog behavioral SPICE model which allows the average temperature of the semiconductor chip of a MOSFET to be determined during a transient simulation is presented. The model is valid for simulation times of less than approximately that of the thermal time constant of the device, and has demonstrated excellent agreement with measured device temperatures. Thermal impedance data required by the model are available from manufacturers' data sheets, so that the model requires no device measurements or characterization. >

As part of the Electron Cyclotron Heating (ECH) Facility upgrade at DIII–D an 8.4 MW Modulator/Regulator Power System was designed and constructed using acquired hardware from the Mirror Fusion Test Facility (MFTF) at Lawrence Livermore National Laboratory (LLNL) program as a foundation.1 Design changes in the feedback control of the modulator/regulator (M/R) was motivated by the need for improved output voltage regulation and improved capability to modulate the output voltage consistent with reference command signals containing modulation patterns (typically square wave). The regulation characteristics of the old ECH M/R power system had previously constrained gyrotron operation due to marginal voltage control loop stability and slow response to voltage step changes. The technical approach was to develop models of the circuit functions of the M/R controller from the circuit diagrams, and then examine the control characteristics using circuit analysis software. MATLAB® Simulink® and Intusoft IsSPICE4® (SPICE) codes were used to examine the control issues. These analysis software tools were used to simulate the controller functions and yielded identical results. The SPICE circuit model was selected as a baseline for future maintenance by the engineering staff. The analysis of the controller model blocks provided the needed information to modify the controller circuits. Changes made to the controller included addition of a voltage feedback loop around the grid driver amplifier for the power tetrode control grid in the M/R, and changes to the feedback loop compensation of the main error amplifier. The implemented revised controller performance matches the model performance predictions remarkably well. This paper describes the circuit models, implementation of the revisions to the controller, and recent operational results.

Simulation and experimental results on the switching behaviour of bulk-barrier diodes

The principle of super-regeneration can be applied to many electronic circuits to achieve large amplifications The advent of the tunnel diode has made available a device which, by virtue of its voltage controlled negative conductance region, can be used as the active element in a simple super-regenerative amplifier. In a tunnel diode super-regenerative amplifier the quenching process, necessary to start and interrupt the oscillations periodically, is simply accomplished by moving the operating point in the current-voltage characteristics from the negative conductance region to the positive conductance region The simplicity of the circuitry associated with the tunnel diode and its low noise capabilities make tunnel diodes super-regenerative amplifiers or detectors very attractive An analysis based on well-established super-regeneration theory shows that tunnel diodes can operate reliably in the super-regenerative mode. The results of the analysis compare with experimental results with good agreement The possibility of utilizing tunnel diode super-regenerative detectors or amplifiers in practical circuitry has boon demonstrated by their incorporation, with good performance, in actual communication circuits.

Vertically stacked two-dimensional van der Waals (vdW) heterostructures, used to obtain homogeneity and band steepness at interfaces, exhibit promising performance for band-to-band tunneling (BTBT) devices. Esaki tunnel diodes based on vdW heterostructures, however, yield poor current density and peak-to-valley ratio, inferior to those of three-dimensional materials. Here, we report the negative differential resistance (NDR) behavior in a WSe2/SnSe2 heterostructure system at room temperature and demonstrate that heterointerface control is one of the keys to achieving high device performance by constructing WSe2/SnSe2 heterostructures in inert gas environments. While devices fabricated in ambient conditions show poor device performance due to the observed oxidation layer at the interface, devices fabricated in inert gas exhibit extremely high peak current density up to 1460 mA/mm2, 3-4 orders of magnitude higher than reported vdW heterostructure-based tunnel diodes, with a peak-to-valley ratio of more than 4 at room temperature. Besides, Pd/WSe2 contact in our device possesses a much higher Schottky barrier than previously reported Cr/WSe2 contact in the WSe2/SnSe2 device, which suppresses the thermionic emission current to less than the BTBT current level, enabling the observation of NDR at room temperature. Diode behavior can be further modulated by controlling the electrostatic doping and the tunneling barrier as well.

The measured I-V characteristics of the double barrier resonant tunneling (DBRT) diode is distorted in the negative differential conductance region if the device is unstable. This paper presents a study of the I-V curve of the DBRT diode in oscillating conditions. This task is fulfilled using an accurate large signal model and PSPICE simulations. First, the PSPICE DBRT diode model is presented. Then the circuit model used for nonlinear simulations is described. Based on the simulation results, concluding remarks with regards to DBRT diode behavior are derived.