A stateless, content-directed data prefetching mechanism

Although central processor speeds continues to improve, improvements in overall system performance are increasingly hampered by memory latency, especially for pointer-intensive applications. To counter this loss of performance, numerous data and instruction prefetch mechanisms have been proposed. Recently, several proposals have posited a memory-side prefetcher; typically, these prefetchers involve a distinct processor that executes a program slice that would effectively prefetch data needed by the primary program. Alternative designs embody large state tables that learn the miss reference behavior of the processor and attempt to prefetch misses.This paper proposes Content-Directed Data Prefetching, a data prefetching architecture that exploits the memory allocation used by operating systems and runtime systems to improve the performance of pointer-intensive applications constructed using modern language systems. This technique is modeled after conservative garbage collection, and prefetches likely virtual addresses observed in memory references. This prefetching mechanism uses the underlying data of the application, and provides an 11.3% speedup using no additional processor state. By adding less than ½% space overhead to the second level cache, performance can be further increased to 12.6% across a range of real world applications.

NVM (Non-Volatile Memory) that gains attention as an alternative memory technology these days has different memory characteristics in terms of latency and bandwidth, compared with the traditional DRAM. In this paper, we analyze how these different characteristics affect the performance of applications. For this purpose, we design a new memory analysis framework that can control the memory latency and bandwidth through hardware and software techniques in commercial computer systems. The framework allows an application to be executed as it is without any modification, leading to fast analysis under diverse configurations. In addition, we devise a novel memory performance model that investigates performance with the viewpoint of LLC (Last Level Cache) and MLP (Memory Level Parallelism). Real implementation based experiments show that our model analyzes performance changes accurately when we compare with the results measured by the proposed framework

Large-scale graph processing is an increasingly important workload in modern systems. Conventional systems are usually optimized for locality of memory references, using caches and parallelization techniques to cover long memory latencies. However since graphs are distributed over memory in unpredictable manner, their processing does not exhibit great locality. While graph algorithms have plenty of parallelism, they are not easily amenable for effective vectorization, as the memory references are scattered all over. What is needed is a paradigm to specify a number of parallel tasks, each of which performs a short computation near the memory and a mechanism to efficiently execute them. In this paper, we propose a novel computational model that is memory-centric: the computation is organized as a collection of functions, each of which operates on a specific piece of data and is executed close to the memory where it resides. Basic primitives are provided to orchestrate the flow, synchronization and execution of the functions at their respective data points to accomplish a global task. We propose a scalable architecture to execute this computational model. We simulate an implementation of this architecture to compare the performance of running some graph algorithms on it with observed performance when the same algorithms were run on conventional systems. Preliminary results for a few graph algorithms show our approach is very promising in improving the performance of graph algorithms.

The memory subsystem is the major performance bottleneck in terms of speed and power consumption in today's digital systems. This is especially true for application specific embedded systems where power consumption due to memory traffic, memory latency and size of the on-chip caches have a significant role in overall system performance, energy efficiency and cost. There is an urgent need of tools that help designers take informed decisions about memory subsystems for embedded applications. This paper presents a novel, fine-grained memory profiling technique that provides the designer with valuable information such as the total amount of dynamic memory requirement of an application, the most heavily accessed source level data objects, the most memory intensive portions of an application etc. Such information can aid designers to take decisions about the overall memory subsystem comprising of a number of different cache levels, scratch-pad memories and main memory. It can also be used by a compiler to perform advanced compiler controlled memory assignment techniques, and by the application programmer to optimize an application. Case studies at the end of this paper demonstrate the accuracy of our profiling technique and provide some example usage scenarios of it.

Due to a late and out-of-order arrival of infinite, unbound and multiple input streams, processing continuous queries over them may lead to producing an inaccurate answer or delaying query execution. Particularly, to minimize this delay time, previous works have used timeout technique without considering the frequency of timeouts. It results in decreasing the accuracy of query execution results since the more the frequency of timeouts, the more the loss of data. We propose a AQP-SWTO method using StB that stores operator's state and a window time-out method based on the waiting time for the next tuple by resetting the size of a queue according to the frequency of timeouts. It reduces a loss rate of data and increases the tuples output-rate. We compare AQP-SWTO method with an existing method and use output-rate and response time as criteria for performance evaluation. As a result of experiment, our proposed method shows an improvement in system performance.

As technology advances both in increasing bandwidth and in reducing latency for I/O buses and devices, moving I/O data in/out memory has become critical. In this paper, we have observed the different characteristics of I/O and CPU memory reference behavior, and found the potential benefits of separating I/O data from CPU data. We propose a DMA cache technique to store I/O data in dedicated on-chip storage and present two DMA cache designs. The first design, Decoupled DMA Cache (DDC), adopts additional on-chip storage as the DMA cache to buffer I/O data. The second design, Partition-Based DMA Cache (PBDC), does not require additional on-chip storage, but can dynamically use some ways of the processor's last level cache (LLC) as the DMA cache. We have implemented and evaluated the two DMA cache designs by using an FPGA-based emulation platform and the memory reference traces of real-world applications. Experimental results show that, compared with the existing snooping-cache scheme, DDC can reduce memory access latency (in bus cycles) by 34.8% on average (up to 58.4%), while PBDC can achieve about 80% of DDC's performance improvements despite no additional on-chip storage.

In the development process of multi-core processors, the Network on Chip optimizes the storage structure, but the problem of “storage wall” still exists. There are many ways to alleviate this problem. The improvement of memory access performance can be obtained for appropriate address mapping between cache levels. As far as the performance index of address mapping is concerned, it can be considered from the perspectives of memory access bandwidth and latency in different levels of the storage system. Therefore, a module-level detection tool is designed to test the memory access performance. Based on the hardware emulation acceleration platform, this tool solves the online/offline data collection of memory access bandwidth and latency. And it implements the functions for extremely long simulation times, which is data capture, analysis, and processing. Under different address mapping and data types of different application scenarios, This tool tests memory access performance between cache modules. Based on the data-affinity address cross-mapping method, this thesis proposes an address mapping optimization scheme that binds the directory controller unit and the local memory. Through the module-level memory access performance test, the optimized data affinity and low-order address cross-mapping method increases the memory access bandwidth by 8% and the maximum bandwidth by 9% when processing scheduling-intensive data. In a word, this thesis establishes the memory access performance analysis method which is “benchmark test program, module-level memory access performance detection, address mapping optimization and configuration”.

Cache misses are becoming relatively more expensive in modern processors. This is largely due do the fact that processor clock rates are increasing faster than the latency of main memory is improving. Prefetch has been used to hide memory latency. There are at least two kinds of prefetches - automatic prefetch and instruction-initiated prefetch. This paper described an implementation-independent instruction-initiated prefetch mechanism for I-cache and an automatic prefetch mechanism for D-cache to hide the memory latency associated with cache misses. Simulation results taken from execution traces of 5 commercial relational database management systems were used to illustrate the potential benefit of the proposed mechanisms.

Prefetching significantly reduces the memory latencies of a wide range of applications and thus increases the system performance. However, as a speculative technique, prefetching may also noticeably increase the number of memory accesses, which in turns may negatively impact on the main memory bandwidth consumption, performance, and power. Main memory bandwidth consumption is a critical resource especially in the context of current multicore processors since memory requests from all the cores, both prefetch and demand requests, compete among them in the access to the DRAM banks. Consequently, demand requests may be delayed hurting the system performance. This work proposes the Activation/Deactivation Policies (ADP) scheme for hardware prefetchers in multicore processors. This scheme relies on activation policies that turn on the prefetcher on a given core when it is expected that prefetches will improve the performance, and turn off the prefetcher of that core when it is foreseen that performance will be scarcely improved or not improved at all. The proposed mechanism effectively reduces the memory bandwidth requirements of some cores with respect to a typical always prefetching mechanism, so making available extra bandwidth to the co-runners. Results in a four-core processor show that ADP prefetching achieves similar performance ±2.5% as always prefetching, while significantly reducing the memory bandwidth consumed by use-less prefetches. Moreover, in some applications this reduction is as much as 50%. ADP prefetching is applicable to stream-based prefetchers, global-history-buffer delta correlation prefetchers, and PC-based stride prefetchers.

Current Chip Multiprocessors (CMPs) consist of several cores, cache memories and interconnection networks in the same chip. Private last level cache (LLC) configurations assign a static portion of the LLC to each core. This provides lower latency and isolation, at the cost of depriving the system of the possibility of reassigning underutilized resources. A way of taking advantage of underutilized resources in other private LLCs in the same chip is to use the coherence mechanism to determine the state of those caches and spill lines to them. Also, it is well known that memory references are not uniformly distributed across the sets of a set-associative cache. Therefore, applying a uniform spilling policy to all the sets in a cache may not be the best option. This paper proposes Adaptive Set-Granular Cooperative Caching (ASCC), which measures the degree of stress of each set and performs spills between spiller and potential receiver sets, while it tackles capacity problems. Also, it adds a neutral state to prevent sets from being either spillers or receivers when it could be harmful. Furthermore, we propose Adaptive Variable-Granularity Cooperative Caching (AVGCC), which dynamically adjusts the granularity for applying these policies. Both techniques have a negligible storage overhead and can adapt to many core environments using scalable structures. AVGCC improved average performance by 7.8% and reduced average memory latency by 27% related to a traditional private LLC configuration in a 4-core CMP. Finally, we propose an extension of AVGCC to provide Quality of Service that increases the average performance gain to 8.1%.

• A new control logic for the SCMSHPD system under low meteorological conditions was proposed. • Performance of the SCMSHPD system operating under the new control logic were analyzed. • The effects of the waste heat recovery on the combined drying system under different meteorological parameters were obtained. • Drying process of the combined drying system was optimized. To solve the problem that the high drying temperature demand could not be met when combined drying system operated under low ambient temperature and weak solar irradiance, a new control logic of the solar combined multi-heat source heat pump drying (SCMSHPD) system was proposed and its simulation model was established. By modifying its operating strategy, the SCMSHPD system achieved a higher drying temperature under low environment temperature and weak irradiance, which ensured the implementation of the drying process. The simulation results was verified through experimental study. Additionally, to address the issue of significant heat loss of the exhaust air, waste heat recovery was implemented and its impact on the system’s operating characteristics was analyzed. At last, the drying process was optimized due to the significant improvement of the specific moisture extraction rate ( SMER ) and the system performance was further improved. The results showed that the errors in coefficient of performance ( COP ), energy consumption, and SMER between the experimental and simulation results were 4.04%, 1.84% and 1.53% respectively, which verified the reliability of the simulation model. In October, the COP of the SCMSHPD system without waste heat recovery was 3.66% higher than that of the ASHPD system, but with the decrease of ambient temperature and solar irradiance, the COP of the combined drying system increased by 5.86% in December, demonstrating the advantage of the SCMSHPD system with the new control logic under low meteorological parameters. The waste heat recovery could not improve the system performance of the SCMSHPD system operating with the new control logic proposed, which caused a decrease of 1.06% and 1.19% in October and December respectively. However, the SMER was significantly increased by 70.67% and 12.78% respectively, and the energy consumption was significantly decreased by 41.33% and 10.94%. The results indicated that although waste heat recovery resulted in a slight decrease in system COP , the significant reduction in energy consumption and notable increase in SMER demonstrated a marked improvement in the overall system performance. Due to the significant increase of the SMER , the drying time was shortened, which caused an increase of 1.77% in COP in October. With meteorological parameters became lower, the COP get a bigger increase of 3.34%. Therefore, it could be concluded that the combination of waste heat recovery and shortened drying time could effectively improve the system performance, and the lower the meteorological parameters, the greater the improvement in the system performance. This study can provide important guidance for the selection of control logic and the optimization of the drying process for the SCMSHPD system under low meteorological parameters.

Effective allocation of shared resources limited is a key problem for chip multiprocessors.As the processor core growth in the scale, multi thread for the shared resource limited system competition will become more intense, the performance of the system will also be more significant.In order to alleviate this problem, a fair and effective multi thread shared resources allocation scheduling algorithm is important.In all kinds of shared resources, the largest effect on the system performance is the shared cache and DRAM system.There are essential differences between the last level cache and a cache.The goal of a cache design is to provide fast data processor which requires high access speed.However, the object of the last level cache is to save data in the chip as much as possible, and the access speed requirements are not too high, it is more subject to the plate number of available transistors.Management level cache LRU strategy and its approximate algorithm are not applicable to the large capacity last level cache for traditional.It may cause destructive interference between threads, cache thrashing of stream media program lead, which will lead to a decline in the performance of processor.This paper focuses on the analysis of some hot problems of the last level cache management in the process of the large capacity of multi-core platform sharing, and puts forward the corresponding costs less.

To realize efficient performance in industrial applications, wireless sensor networks (WSNs) have witnessed routes developed. In WSN operations, it is important to note that they rely upon and operate on battery, which implies that there is energy restriction. In the current study, the aim was to design a routing protocol through which improved WSN energy conservation could be achieved, hence preserving the battery life. In the study, three variables were on the focus and aided in making informed decisions about routes that would be deemed appropriate. These parameters included the distance needed for the successful sending of packets to the destination node (from the source and in meters), the traffic amount in Erlang, and the sensor energy in joules. In the proposed routing protocol, it is important to note that it was based on FACO (fuzzy logic and ant colony optimization). Indeed, the role of employing fuzzy logic lay in the calculation of the total cost of the node–gateway intersection relative to the node’s energy, as well as its traffic load. Similarly, the implementation of ACO was informed by the need for searching and establishing distances that would prove the shortest between the sources to the destination sensor nodes, with the shortest distances aiding in system performance evaluation and inference-making. With MATLAB simulation adopted, findings demonstrated significant improvements in system performance, especially in terms of energy conservation. Particularly, results from FACO implementation, relative to the energy conservation parameter, suggested its superiority, as it outperformed ACO, having implemented the two algorithms under the same experimental conditions and with the same experimental parameters. The future implication for industrial applications is that the routing algorithm associated with system improvements via more energy conservation could be implemented via the use of WSN.KeywordsRouting optimizationEnergy conservationACOFACOWSN

The semiconductor industry is continuously evolving to meet the demands of an increasingly connected and data-driven world. As traditional Moore's Law scaling becomes more challenging, the next frontier in advanced packaging is heterogeneous integration (HI), with an emphasis on key technologies such as silicon interposers, hybrid bonding, and fan-out wafer-level packaging (FOWLP). HI involves combining various components and technologies, including diverse materials, devices, and functions, within a single package to enhance system performance, functionality, and miniaturization. This paper explores the emerging paradigm of heterogeneous integration with a focus on these key enabling technologies. I will discuss the principles and capabilities of silicon interposers, which provide a versatile platform for integrating different semiconductor components, reducing interconnect length, and enhancing signal speed and power efficiency. Hybrid bonding, a revolutionary technique for precise, low-temperature chip-to-chip connections, is another critical aspect, enabling a new level of flexibility in the assembly of complex systems. Furthermore, I will examine the advantages and versatility of Fan-Out Wafer-Level Packaging (FOWLP), which enables the integration of multiple semiconductor devices and heterogeneous components on a single wafer. This approach not only reduces form factors but also offers cost-effective and high-performance solutions for a wide range of applications. This paper discusses how the synergy of silicon interposers, hybrid bonding, and FOWLP has brought about the benefits of HI, such as improved system performance, cost-effectiveness, and time-to-market acceleration. These technologies enable the industry to address the challenges posed by the limitations of traditional scaling, enhancing system capabilities and performance in various applications, including high-performance computing, artificial intelligence, 5G communications, automotive electronics, and healthcare devices. An overview of these three core HI platforms will be presented along with applications areas.

As analyses of system behavior and complexity through computer modeling and simulation have been growing, high performance modeling is noticed to handle behavior and complexity of modern large-scale systems. The high performance modeling focuses on high resolution representation of system and performance improvement. This paper presents a quantized system modeling as an effective high performance modeling. The quantized system modeling represents state resolution using state quantization and improves system performance through message filtering among system components. This paper realizes a practical quantization component which is based on both of Discrete Time System (DTS) and Discrete Event System (DES) and shows usefulness of quantized system in a variety of industrial applications. This paper models a real-world application, e.g. a space traveling system with the quantized system and evaluates system performance, accuracy, and scalability of the quantized system on DES-based modeling and simulation.KeywordsMessage PassingDiscrete Time SystemDiscrete Event SystemInput EventQuantization ApproachThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.