A Study on Optimized SiC Half Bridge Through PCB Embedding

Tuncay Duman; Oliver Koenig; Christoph Abart; Roland Greul; Jue Chen; Ales Chvala; Juraj Marek; Alexander Satka

doi:10.1109/ecceeurope62508.2024.10751847

Sep 2, 2024
Tuncay Duman +7 more

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Abstract

To demonstrate the benefits of advanced PCB manufacturing technologies in power electronics, this study presents a PCB embedded SiC half bridge design and compares its switching transients with the conventional SiC package design. The presented PCB embedded design stands out as a compact design, occupying nearly 40 % less space compared to the conventional design. The silver sintered die attached copper lead frame, low thermal resistivity prepreg, and copper filled laser microvias provide an effective thermal conductivity between die and the cooling side of the PCB. The compact design also ensures the power loop inductance below 1.5nH at 1MHz and, compared to conventional SiC package design, offers five times less parasitic PCB capacitance. The experimental results show that the switching speed of the designs are 19 V/ns and 15 V/ns during turn on transients, and 8 V/ns for both during turn off transients. The lower overshoot stress and faster damped ringing in PCB embedded design contribute to the reduction of the switching losses.

Conference Article
1
10.1109/icsj59341.2023.10339574

Prototyping and Evaluation of SiC Half Bridge Circuit Using Power Device Embedded Module Process Towards Future Three Dimensional Packaging

Nov 15, 2023
Kazuhito Nakamura + 3 more +3

Recently WBG (Wide Band Gap) power semiconductors such as SiC and GaN, which have been attracting attention, are being applied in power electronics field because of their high switching speed and low losses compared to existing Si power devices. SiC is spreading from industrial applications to main traction systems of N700S SHINKANSEN bullet trains, and GaN is spreading to low-voltage applications such as AC adapters, DC/DC converters and LED drivers etc. . On the other hand, there are problems such as surge noise due to current path stray inductance Ls by high current reduction rate, di/dt, at turn-off. To reduce the turn-off voltage surge, it is necessary to optimize structure of main current path to minimize Ls. In optimizing the structure, loop inductance can be reduced by forming a return path in which current distribution could cancels leakage magnetic flux. However, depending on the switching mode of the power converter topology, such as a three phase inverter, the main current may not always be a return path that cancels the leakage magnetic flux. This time, in order to confirm the usefulness of Power Device Embedded Module (POWER DEM) packaging process, a prototype of SiC bare die embedded half-bridge circuit has been prototyped. Inductance analyzed results of circuit structure using ANSYS Q3D Extractor® before prototyping, have been comparatively evaluated. As a result, loop inductance was 5.5 nH in Q3D analysis, 3.6 nH in impedance analyzer, and calculated inductance from actual surge voltage was 10.03 nH. Finally, turn-off voltage surge, turn-on loss, turn-off loss, turn-on time and turn-off time have been reduced approximately 40 % to 80 % compared to similar half bridge circuit using conventional TO-247 packages. Further works are to optimize current path constructions for actual cases of circuit topologies i.e. three phase inverter etc., modeling of three dimensional structure including dielectric insulating material and analyze methods.