A Study on the Development of Simulating Tool for Evaluation of Electrostatic Discharge

The ESD Effect Experiment of the Integrated DC-DC Transformer

Electrostatic Discharge (ESD) events can cause irreversible damage during production, packaging and application of Vertical-Cavity Surface Emitting Lasers (VCSELs). Experimental investigation of those damage patterns inside a real device is a complex and expensive task. Simulation tools can provide insight into the physics during an actual discharge event. This paper aims to analyze ESD events in VCSELs with a microscopic simulation. With the help of a state-of-the art Technology Computer Aided Design (TCAD) virtual ESD tests are performed on oxide-confined VCSELs. The 2-D simulation model takes into account high-field effects and self-heating in a hydrodynamic framework that allows time-dependent spatially resolved monitoring of critical quantities (such as electric field across the oxide, temperature profile, current densities) during the ESD events. Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM) show typical local heating and current crowding effects which may lead to irreversible damaging of the device. For slow ESD events the temperature peak is found near the center of the device. Faster pulses show maximum temperature at the interface between oxide and aperture. Physics-based explanations in terms of local electric field, heat generation and heat transport are given. Oxide aperture, thickness and its position relative to the intrinsic region strongly influence self-heating, electric fields, current density profiles and the dielectric breakdown conditions. The impact of those factors on ESD robustness are analyzed and guidelines for robust ESD design in VCSELs are presented.

Optimization of a 3.3-V/ 5.0-V tolerant electrostatic discharge (ESD) protection network for both diffused n-well/LOCOS and retrograde well/shallow trench isolation (STI) CMOS technologies in a RISC microprocessor is discussed. ESD-related semiconductor-process key design features, ESD circuit operation, data, simulation and failure analysis are presented. ESD robustness of 4000-V human body model (HBM), 400-V machine model (MM), and 1500-V charge device model (CDM) is achieved in both technologies using a common design. >

A string of failures discovered during final testing after assembly led analysts on a long search for the cause, which turned out to be an unusual form of electrostatic discharge (ESD). Most ESD impacts on ICs occur by way of the pins. Nearly all ESD models, including the widely used human body model, charged-device model, and machine model, are based on this assumption. However, as this case study proves, passivated wafers and unpackaged dies are also susceptible to ESD damage. The authors explain that although this type of failure is difficult to diagnose, they were able to pinpoint the cause using lock-in microthermography and rule out mechanical-, FIB-, and laser-induced failures, which are similar in appearance.

Analysis of charge injection processes including ESD in MEMS

Optoelectronic components such as laser diodes, light-emitting diodes, and photodiodes are susceptible to electrostatic discharge (ESD) and electrical overstress (EOS). Human-body model (HBM) is the most widely adopted method for the characterization of the ESD performance. In this paper, we report a comprehensive study of the ESD and EOS characteristics of buried-heterostructure (BH) semiconductor lasers using the HBM. Threshold current, optical power, optical spectrum, and reverse-bias current are characterized during the ESD study. We show that the ESD-failure thresholds depend upon the polarity. The chip can sustain the highest ESD stress under forward bias and the lowest one under forward/reverse bias. We also show that the BH lasers exhibit two types of ESD-degradation behavior. The soft degradation is characterized by a gradual increase in the threshold current, whereas the hard degradation is identified by a sudden jump in the threshold current during the ESD voltage ramp. The ESD-degradation behavior seems to be influenced by the cavity length. The failure-analysis results show that about 27% of the ESD failure is related to facet damage. The damage regions occur at the upper laser mesa structure and form preferentially on the bond-pad side. The preferential formation of the facet damage is suggestive of current-crowding effect. We have also found that the ESD-degradation behavior is a function of the facet damage. The soft-degradation failure shows a stronger correlation with the facet damage than the hard-degradation one. Finally, we demonstrate that the ESD performance of the laser can be improved by adding a protection diode.

An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.

In order to protect electronic products from Electrostatic Discharge (ESD) damage, multi-layer ceramic capacitors (MLCC) are often used to bypass the transient ESD energy. Most dielectric materials used in MLCC are nonlinear, since the dielectric constant decreases with increasing voltage, reducing the capacitance value, thus degrading the ESD protection effect. Using a large initial capacitance value will ensure sufficient ESD protection; however, the shunt capacitors also limit the signal bandwidth of the ESD-protected data channel, thus setting a maximal capacitance value at data voltage levels. This paper investigates the nonlinearity of capacitors and suggests improved tradeoff between ESD protection and data bandwidth by using the Antiferroelectric (AFE) capacitors as ESD protection. The dielectric constant of AFE material increases with increasing voltage. The voltage dependence of X7R and AFE capacitors are measured using static and nanosecond transient measurements. The ESD protection effectiveness with different material capacitors are compared by simulation. Due to very limited availability of suitable AFE material samples only hand-made capacitors have tested without investigating the long term stability of the material.

In the implanted biomedical devices, the silicon chips with monopolar stimulation design have been widely applied. To protect the negative-voltage pins of the implanted silicon chip from the electrostatic discharge (ESD) damage, the ESD protection circuit should be carefully designed to avoid any wrong current path under normal circuit operation with the negative voltage. In this article, a new power-rail ESD clamp circuit for the application with an operating voltage of -6 V has been proposed and verified in a 0.18-μm 3.3-V CMOS process. The proposed-circuit, realized with only 3.3-V nMOS/pMOS devices, is able to prevent the gate-oxide reliability issue under this -6-V application. With the proposed ESD detection circuit, the turn-on speed of the main ESD clamp device, which is a stacked-nMOS (STnMOS), can be greatly enhanced. The STnMOS with a width of 400 μm can sustain over 8-kV human body model (HBM) ESD stress and perform low standby leakage current of ~5.4 nA at room temperature under the circuit operating condition with -6-V supply voltage.

An ESD protection circuit in chip level protection is proposed as the electrostatic discharge (ESD) clamping circuit such as thick field oxide (TFO), grounded gate MOS (GGNMOS) and separated segment for input protection. The ESD protection circuit for input protection was implemented from the proposed ESD protection circuit. The GGNMOS applied to separated segment has been simulated by DESSIS of TCAD for thermal characteristic with human body model (HBM) pulse and realized the protection circuit for input protection has been simulated by HSPICE.

Above-IC inductors enable low-power RF circuit design, and in addition efficiently protect the RF pins against electrostatic discharge (ESD) stress. This is demonstrated using above-IC inductors in the design of a fully integrated 5 GHz ESD-protected LNA and VCO in 90 nm CMOS. The LNA without ESD protection shows 1.4 dB NF, with 18 dB gain, drawing 4 mA from a 1.2 V supply. The ESD protected LNA has a 2.2 dB NF and 17.6 dB gain while sustaining human body model (HBM) ESD stress of above 8 kV. The 5.4 GHz VCO has a current consumption of 150 muA with a 1.2 V supply, and a 10 % tuning range with a worst case phase noise of -111 dBc/Hz at 1 MHz offset

This paper presents the general and analytical solution of a fourth‐order lumped element model (LEM) to describe human body model (HBM) electrostatic discharge (ESD) testers including the main tester parasitic elements. The analytical fitting to the LEM of experimentally obtained HBM pulse data is a new scientifically justified tool to determine HBM tester parasitic elements. The impact of the test board capacitance on HBM testing is demonstrated and explained. Furthermore, the MIL 883C/3015.71 and EOS/ESD S5.1‐19912 Standards on HBM testers are evaluated upon their selectivity to the test board capacitance. Finally, recommendations to improve HBM tester specifications regarding their selectivity to the parasitic test board capacitance are formulated

The drain-to-source HBM (human body model) ESD (electrostatic discharge) robustness of GaN HEMTs has been investigated through the TLP (transmission line pulse) I-V tests in most previous works. However, TLP tests and HBM ESD tests are found to be miscorrelated using the conventional method applicable to Si MOSFETs. In this work, it is found that the drain-to-source breakdown mechanism of GaN HEMTs contradicts the basis of the conventional correlation method, which also leads to much longer rise time of the drain-to-source voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> ) in the HBM ESD test than in the TLP test. Therefore, the HBM ESD test of GaN HEMTs is correlated with a pulse I-V (PIV) test with easily adjustable rise time to establish a more suitable method. The HBM ESD sensitivity is estimated from the PIV test with an error of 4.5%.

Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a computer-aided design tool for ESD protection design and applications. Specifically, we develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. Experimental data measured from the transmission line pulsing (TLP) technique and human body model (HBM) tester are included in support of the model.