A survey on defect detection in bare PCB and assembled PCB using image processing techniques

Printed circuit board (PCB) assembly lines consist of a number of different machines for mounting electronic components onto PCBs. While high-speed placement machines are employed to assemble standard components, so-called fine-pitch placement machines are used to mount complex electronic components with high precision and by use of specific nozzles. In this paper, we investigate a typical mass production environment where a single type of PCB is assembled in a line comprising high-speed as well as high-precision placement machines. The PCB assembly line balancing problem consists of assigning component feeders, each holding a specific electronic component type, and the corresponding placement operations to machines in the line so as to minimize the assembly cycle time. To solve this problem, a two-stage solution procedure based on genetic algorithm (GA) is proposed. In the first stage, component feeders are assigned to the placement machines with the objective of balancing the workload within the assembly line. A number of candidate solutions are then transmitted to the second stage, where specific machine optimization algorithms are applied to determine the feeder-slot assignment in the component magazine of the machines and the placement sequence of the various components. As a result, fine-tuned placement operation times are achieved which reflect the individual operation mode and the actual component setup of the placement machines. Finally, from the candidate solutions the one which minimizes the actual PCB assembly time is selected.

Process planning output can be post-processed into criteria for job scheduling decisions in printed circuit board assembly using surface-mount technology (SMT). Artificial intelligence-based techniques used in computerized planning and scheduling systems in other industries can be extended to printed circuit board operations. These techniques include blackboard architectures, object-oriented programming systems, and nonmonotonic reasoning systems. These techniques were used to demonstrate a unique architecture of blackboard systems that communicate via object-oriented messages to arrive at a shop-floor process plan and production schedule. The methodology was specialized to the assembly of printed circuit boards using surface-mounted components in a high-variety/low-volume product mix. The assembly facility was represented as a hierarchical object of product, process, and organizational knowledge. The system of working heuristics was integrated within a prototype environment with the practitioners that assisted in its development. The end result is a good working methodology for system development, implementation, and maintenance by knowledge worker involvement.

The process of manufacturing printed circuit boards and printed circuit board assemblies is very complex. There are numerous process variables with all levels of interactions. These interactions can be difficult to understand and control within a printed circuit board manufacturing facility or printed circuit assembly manufacturing facility. When the interactions span facilities and companies, it takes understanding and controls to prevent latent defects from occurring downstream. What happens when a defect appears that is new, unique and different enough from the typical defect that it is not readily apparent what caused the defect and whether it was caused during the printed circuit board manufacturing process, during the assembly process or, in fact, by an interaction between the two processes? A unique plated-through-hole solder void which did not meet IPC Class II printed circuit board Workmanship requirements as per IPC A610, Acceptability of Electronic Assemblies, occurred on a large number of assemblies.1 There are several questions which immediately arise: What caused the defect? Is the product acceptable for customer shipment? Can the defective product be reworked? Is this a seasonal defect (e.g. laminate voids caused by high levels of moisture in the laminate) or has a variable in the process shifted? A team of engineers from multiple companies worked together to answer these questions.

A knowledge-based system (or an expert system) embodies a domain expert’s knowledge and problemsolving strategy. Domain specific knowledge-based systems formalise the complicated set of informal procedures understood by experts alone and make the expertise available to a wide range of people. Knowledgebased systems have been developed and used in fields as diverse as medicine, mineral exploration, and chemistry. They have been used in various engineering applications and extensively in manufacturing. This paper reviews the application of knowledge-based systems in the Printed Circuit Board (PCB) assembly domain. In keeping with the initial development of knowledgebased systems in the field of manufacturing, most of the current applications of knowledge-based systems in PCB assembly address issues related to process planning. This trend can be attributed to the diversity and short life cycles of electronic products, and shortage of human expertise. A few systems have been developed for PCB design. Developments in the field of electronics packaging and industry predictions lead us to believe that knowledge-based systems will be developed for many more applications within the field.

Process planning is a critical function in any manufacturing domain. This is especially true in the electronics manufacturing area where substantial heuristic and experiential knowledge is commonly used during process plan development. While research in computer-aided process planning (CAPP) has tended to concentrate in the machining realm, few CAPP systems have been developed for electronics manufacturing applications and more specifically for the printed circuit board (PCB) assembly domain. Besides, the CAPP systems that have been developed for this area have dealt with either insertion mount or surface mount PCB assembly processes only.

A production scheduling problem for printed circuit board (PCB) assembly with multiple lines is addressed. The investigated problem is to schedule a set of PCB assembly jobs with different ready times and due dates on multiple assembly lines, with the objective to minimize the sum of total weighted tardiness of jobs and weighted makespan. The feature that each job can be completed by different lines with different process times makes the problem a special type of unrelated parallel-machine scheduling problem (PMSP) with special constraints and a unique objective. A mixed-integer linear programming model for the problem is established and verified through solving some small-sized problem instances to optimality. In order to solve the real-world problems, a steady-state genetic algorithm with an improved replacement strategy is proposed. Experimental tests and a case study are conducted to examine the usefulness and effectiveness of the approach.

10 - Dynamic deformation of a printed circuit board in drop-shock

The purpose of this paper is to study the temperature effect on the Print Circuit Board (PCB) and the solder joints in the vehicle under working condition of the engine. Thermal-stress test has been used to evaluate the reliability or fatigue life of the PCB using commercially available Finite Element Analysis software, ANSYS. The thermal deformation distribution of the PCB and stress of the solder joints can be obtained. The modal analysis was carried out under the thermal and normal condition. The frequency, mode shapes, deformation and stress were obtained. It is observed that the frequency of the overall PCB assembly was decreased under thermal condition as compared to that under normal condition. The position of maximum temperature was located around the top edge of solder joints, which was close to package. And the position of maximum deformation and stress was also located around the top edge of the solder joints, which was close to package. This paper obtains the thermal stress and thermal deformation of the PCB and solder joints in the vehicle and compare the frequency of the PCB assembly under the thermal and normal condition.

A profile identification system for surface mount printed circuit board assembly

In this paper, a research on fatigue life estimation methods for printed circuit board assemblies (PCBA) under vibration loading is conducted. It mainly makes a comparison on fatigue life estimation results, for a FBGA mounted on the center of printed circuit board (PCB) with simply supported on all four sides and subjected to random vibration loading, between Steinberg's model and three-band method. Because Steinberg's model is a practical empirical model based on Steinberg's testing and experience, and the reference of cycles to failure, N1, based on 3s PCB displacement is an empirically determined value and uncertain for new products, using FEA to calibrate the parameter is meaningful for rapid fatigue life estimation. A finite element analysis (FEA) by ANSYS Workbench is performed to obtain the PCBA's natural frequency and the 1-s level von Mises stress of critical solder ball of the component. Using the results of FEA, the fatigue life or damage can be calculated by Steinberg's two methods. And according to the damage equivalent principle, the Steinberg's model (empirical formula) is modified to fit new PCBA's fatigue life estimation and will be verified by test in the next work.

In the actual industrial production environment, the surface defects of products are subtle, and the number of different types of defect data samples is also quite small. Most deep learning models rely on a large number of training samples and parameters to achieve high-precision defect detection. At the same time, the edge computing layer in the actual industrial environment may also encounter transmission delays and insufficient resources. Training a proper model for a specific type of surface defect while simultaneously satisfying the real-time accuracy of defect detection is still a challenging task. To effectively deal with the above challenges, we propose an edge-cloud computing defect detection model based on the intrinsic mean feature detector in the Lie Group space. The modules in the model adopt a symmetrical structure, which can extract related features more effectively. Different from existing models, this model utilizes the Lie Group space intrinsic mean feature as a metric to characterize the essential attributes of different types of surface defects. In addition, we propose an intrinsic mean attention mechanism in the Lie Group manifold space that is easy to implement at the edge service layer without increasing the number of model parameters, thereby enhancing the detection performance of tiny surface defects. Extensive experiments on three publicly available and challenging datasets reveal the superiority of our model in terms of detection accuracy, real-time detection, number of parameters, and computational performance. In addition, our proposed model also shows competitiveness and advantages compared with state-of-the-art models.

In the machining of precision components, a range of defects, including scratches, pits and uneven materials, will inevitably manifest on the surface of the components. Such defects not only result in a reduction in the quality and precision of the parts, but also have an impact on the overall quality, performance, and longevity of the equipment. It is therefore of particular importance to implement effective detection and repair procedures for surface defects in parts. The implementation of efficient detection methods enables the identification and rectification of defects in a prompt and effective manner, thereby ensuring the reliability and long-term stability of the equipment. In this work, we propose a deep neural network-based model that utilises deep convolutional neural networks (DCNNs) to extract features on the surface of parts, and gradually extracts the spatial and textural features of images through multiple convolutional layers and pooling layers. Subsequently, the aforementioned features are fed into the fully connected layer, where complex feature representations are further learned. Finally, the accurate classification of defect types is achieved through multilayer neural networks. The model is thus capable of effectively capturing and identifying different types of surface defects, thereby improving the accuracy and efficiency of identification. The experimental analysis demonstrates that the model exhibits high accuracy and robustness in the identification of different types of defects, thereby verifying its effectiveness and reliability in practical applications.

A heuristic-based model (HBM) that emulates the decision-making process involved in microsequencing components for printed circuit board (PCB) assembly is presented. The model uses a heuristic approach that combines the computer power with the reason

The objective of this research is to reduce the defects in the manufacturing of Printed Circuit Board (PCB) Assembly according to the case study company's issue. The defects from this process must be repaired by the operator and the repairing process becomes waste. The defects occur from the PCB assembly with the Reflow soldering process. The Six Sigma approach with the Design, Measure, Analyze, Improve, and Control (DMAIC) methodology is applied to define the problem and make the main problem focused. The defects are collected as data from the Daily Process Confirmation Record. The cause-and-effect diagram is used to clarify the possible factors to examine. Furthermore, the Design of the Experiment is applied to analyze the significant factors that cause the defects. The 2k Centre points design is used to test the significance of factors. It is observed that after changing only one factor, i.e. solder paste's preparation, the defects are reduced from 5.80% to 0.00%. Not only are the defects reduced significantly but also the man-hour is reduced too. Furthermore, it is anticipated that the repair time will be reduced from 116 hours to less than 50 hours.

Component placement is one of the most time-consuming operations in printed circuit board (PCB) assembly and dominates the cycle time of any PCB assembly line. In our study, we focus on collect-and-place machines which first collect a number of electronic components from the component magazine and then place them one-by-one onto the PCB. With this type of machinery two problems arise, i.e. generating placement tours and determining the placement sequence within each tour. To solve these problems, an effecient clustering algorithm to create placement tours and two modified nearest neighbor algorithms (MNNHs) to determine the placement sequence are proposed. The objective is to minimise the assembly cycle time per board. Numerical experiments show that high-quality solutions are obtained within very short CPU time.