A synchronous latency-insensitive RISC for better than worst-case design

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65nm gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of response surface methodology (RSM) using design of experiments (DOE) and least squares method (LSM), are employed to generate a for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by at least 6X on a normalized basis, against worst case design

Contradictory trends in the industrial design environment have increased uncertainty while decreasing the tolerance to uncertainty. Worst case design techniques, still widely used in industry, do not provide the accuracy required to design under these conditions. On the other hand, statistical design techniques do provide a significant improvement in accuracy, by virtue of their adaptive behavior, but at a substantial cost in computational effort. One practical solution to improving the accuracy of worst case design without sacrificing efficiency is considered here. It integrates an efficient statistical circuit simulator with worst case design tools into a hierarchical performance design process. It employs two stages of worst case analysis, calibrated with statistical circuit simulation, serving as filters to screen out circuits that easily meet their performance requirements. This focuses the use of statistical circuit simulation on those circuits for which the improved accuracy provides significant benefit. This methodology has been applied with outstanding results in design and manufacturing. >

In this paper, CASCADE, a standard supercell-based design methodology, its supporting automated design flow, and associated design tools, are presented for 3D implementations of a class of interconnect-heavy application-specific very large-scale integrated circuits. In CASCADE, a system is first partitioned and synthesized using standard 2D design tools to a set of supercells with the same height and varying widths. With this, the 3D design is reduced to 3D supercell placement and 3D-via assignment. A congestion-driven simulated-annealing method is used to find a 3D placement of supercells to minimize the total wire length, the longest wire length, and the number of 3D vias and routing density. To efficiently estimate the routing density of a 3D grid space within the optimization loop, a simple probabilistic congestion model with an incremental congestion computation has been developed. Once the supercell placement is fixed, the problem of assigning 3D vias to accomplish minimal 2D routing densities and uniform 3D-via distribution is solved by an efficient min-cost-max-flow method. The proposed methods have been implemented and tested on a set of ISPD98 circuit benchmarks. Experimental results have shown that the proposed congestion-driven 3D supercell placement and flow-based 3D-via-assignment tools have yielded satisfactory placement with small-area, low-congestion, short-wire-length, few, and uniformly distributed 3D vias. Furthermore, an excellent correlation between routing-density estimation by our model and the actual routing performed by a commercial router has been observed. We have applied the proposed 3D design methodology, tools, and flows to tape out an over 4-million-gate low-density parity-check decoder in a three-tier 0.18- fully depleted silicon-on-insulator 3D CMOS process manufactured by MIT Lincoln Laboratory. The postlayout simulation of this DRC-clean layout design showed an about ten times improvement on the power-delay-area product compared to a 2D implementation in the same process.

Better-Than-Worst-case (BTW) design has been proposed as an alternative way to operate a circuit by deliberately allowing timing errors for rare cases and rectifying them with error correction mechanisms in order to achieve higher performance, better reliability guarantee, or lower energy consumption. This new design methodology necessitates the analysis and manipulation of signal probabilities during circuit optimization. This paper looks for the solution from the logic synthesis perspective and proposes a new concept, called Common Case Promotion (CCP), to enable effective circuit optimization following the BTW design methodology. CCP consists of: 1) probability-driven re-synthesis that changes a digital circuit's internal structure, 2) a dynamic behavior aware SAT-based redundancy remover that reduces area overhead, and 3) a timed characteristic function (TCF) based circuit dynamic behavior analyzer that provides optimization convergence. The experimental results show that, on average, we can effectively improve circuits' timing error resilience by 24%, which reduces the need of error recovery for BTW circuits considerably, and we can improve the overall energy efficiency by 15%.

Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware components. This is severe in the case of memory components as minimum sized transistors are used in their design. In this work, by considering on-chip data caches, we study the effect of access latency variations on performance. We discuss performance losses due to the worst-case design, wherein the entire cache operates with the worst-case process variation delay, followed by process variation aware cache designs which work at set-level granularity. We then propose a technique called block rearrangement to minimize performance loss incurred by a process variation aware cache which works at set-level granularity. Using block rearrangement technique, we rearrange the physical locations of cache blocks such that a cache set can have its "n" blocks (assuming a n-way set-associative cache) in multiple rows instead of a single row as in the case of a cache with conventional addressing scheme. By distributing blocks of a cache set over multiple sets, we minimize the number of sets being affected by process variation. We evaluate our technique using SPEC2000 CPU benchmarks and show that our technique achieves significant performance benefits over caches with conventional addressing scheme

Mobility degradation and device scaling limitations have led process engineers to develop new techniques that introduce mechanical stress in MOSFET channels, which results in enhanced carrier transport. New fabrication steps strive to increase carrier mobility which, consequently, increases both Ion and Ioff in CMOS devices. However, most stress-enhancement techniques are dependent on layout parameters and their effects can be exploited within standard cell library design. In this work, we propose a new standard cell library design methodology that shares VDD and VSS source/drain connections across standard cell boundaries. Such sharing allows for increased channel stress in both the corresponding device as well as its neighboring devices. Using an industrial 65 nm process and standard cell library, we show that our standard cell design methodology can be seamlessly integrated into current, state-of-the-art digital IC design flows. The new shared source/ drain technique improves critical path delay by 11% on average over a number of benchmarks for only a ~35% increase in leakage. Furthermore, stress-enhanced standard cell libraries offer a superior power/ delay tradeoff compared to dual-Vth across a wide range of operating points with reduced manufacturing costs. Specifically, our stress-enhanced library (with a single Vth) consumes ~2.5X less leakage than its dual-Vth counterpart.

Parameter variations have emerged as a significant threat to continued CMOS scaling in the nanometer regime. Due to increasing performance penalties associated with worst-case design, recovery based design has emerged as a promising approach for dealing with the impact of variations. Previous work has applied recovery based design at the circuit and micro-architecture levels of abstraction. In this work, we address the problem of designing variation-tolerant SoCs using the recovery based design paradigm. We demonstrate that a monolithic implementation of recovery based design fails to scale for large SoCs. We propose the concept of recovery islands, wherein each island consists of one or more SoC components that can recover independent of the rest of the SoC, and demonstrate how our proposal can be easily realized via minor changes to a traditional SoC design flow. We study the tradeoffs involved in applying recovery based design at the system level. We demonstrate that it is critical to account for (i) the inherent diversity of the error-voltage profiles among various components in an SoC, and (ii) the impact of error recovery in a component on overall system performance. We then propose a systematic recovery-based SoC design methodology that partitions a given SoC into recovery islands and also computes the optimal operating points for each island, taking into account the various system level trade-offs involved. We evaluate our framework on three different SoC designs, an 802.11b MAC processor, an MPEG encoder and a Wireless Video Capture system and demonstrate an average of 32% energy savings over conventional designs.

Manufacturing has been incapable of keeping up with Moore's law without significantly increasing process variability and imposing massive geometric restrictions on design. This paper highlights the design impact of variability and geometric constraints - including traditional design rules and pattern-scale constraints - and describes our approach for evaluating and enforcing pattern-scale restrictions on design.

Relational databases: a theoretical primer

In this paper we describe those aspects a designer has to take into account when designing Web-based adaptive courses with TANGOW. The discussion is specifically focused on the adaptivity issues, which are not covered by any standard design methodology. The first section describes the decisions that need to be made in order to create adaptive courses by using TANGOW. Work done on some approaches to facilitate the design of Web courses is presented next. The paper finishes with some conclusions and work in progress.

3064 Background: The primary goal of oncology phase I trials is to determine the maximum tolerated dose (MTD) in a small number of patients. Within the standard design methodology currently employed there remains many challenges and one pertains to the variability around defining dose limiting toxicities (DLTs). The pre-specified DLT criteria may not well reflect the clinician’s practical experience with some adverse events, while others may actually be related to the disease status more than the investigational drug and could be misclassified. DLT misclassification seen in testing a small sample size from each dose group could generate a large bias on dose finding and the MTD estimation. Methods: To mitigate the risk of dichotomizing and misclassifying DLTs, we proposed a strategy that introduced the new concept of “equivocal” DLT or AE. A novel dose escalation approach is applied to increase the variability associated with less interpretable AEs so that the model recommendations are more weighted towards the unequivocal AEs/DLTs. To evaluate this novel approach, we established a framework incorporating two types of systematic measurement errors on DLT misclassification, one for the misclassified DLT that is not related to the drug treatment while the other for the non-DLT AE that should be considered severe and relevant to dose finding. In our simulation studies, the Bayesian logistic regression model (BLRM) was used to guide dose escalation in simulated trials to compare the novel weighting approach with the traditional approach. A few numerical examples were also included for method illustration. Results: For different types of measurement errors, simulation studies showed that the weighting approach could successfully improve the trial performance, with higher chance of finding the correct MTD and treating more patients at the MTD level. Conclusions: The DLT weighting strategy provides a flexible but powerful tool that may incorporate the clinician’s valuable experience on some specific DLTs/AEs and improve MTD estimation in oncology phase I dose-escalation trials.

General background: The growing demand for high-quality paving blocks in Indonesia requires manufacturers to consistently meet SNI standards, particularly in compressive strength, as it determines durability and safety. Specific background: At PT. XYZ, production inconsistencies often lead to cracks during testing, highlighting variability in process parameters. Knowledge gap: Although the Taguchi method has been widely applied in manufacturing quality improvement, its systematic integration with multiple critical parameters in paving block production remains underexplored. Aim: This study seeks to optimize compressive strength by applying the Taguchi Design of Experiments with an L₉ orthogonal array, focusing on cement–sand ratio, fly ash content, and aggregate size. Results: Signal-to-Noise Ratio and ANOVA analyses revealed that cement–sand ratio is the most influential factor, followed by fly ash and aggregate type, with the optimal combination of 3:5 cement–sand ratio, 3% fly ash, and medium aggregate (5–10 mm), producing a compressive strength of 42.16 MPa—exceeding the SNI minimum of 40 MPa. Novelty: This research introduces a robust model that integrates Taguchi and ANOVA to validate optimal production parameters specifically for paving block manufacturing. Implications: The findings provide practical guidelines for improving product consistency, reducing defects, and supporting cost-effective quality engineering in the paving block industry. Highlights: Taguchi design identified optimal cement–sand ratio, fly ash, and aggregate size. Optimal parameters achieved 42.16 MPa, exceeding SNI standards. Integration of Taguchi and ANOVA ensures consistent, cost-effective quality control. Keywords: Paving Block, Compressive Strength, Taguchi Method, ANOVA, Quality Engineering

This work presents a complete deep-learning-driven automation flow for designing ultra-low-power subthreshold operational transconductance amplifiers used in electronically tunable gm-C resonator and anti-resonator circuits for speech vowel processing. A multi-task learning neural network is trained as an accurate and extremely fast metamodel (surrogate) of an 8-parameter operational transconductance amplifier topology in 350 nm CMOS process node. Using only 60000 Latin-hypercube-sampled circuit simulations for training, the metamodel predicts DC power consumption, total transistor area, and DC transconductance with average errors of 2.9%, 5.0%, and 7.3%, respectively. The trained model is then coupled with the NSGA-II multi-objective genetic algorithm to instantly generate Pareto-optimal trade-offs between power and area for any designer-specified gm value in the 45-55 nA/V range typical of vowel formant filters. Compared to conventional simulation-in-the-loop NSGA-II optimization, the proposed flow reduces the total design time from 25 h to 7 h, a 3.5 times speedup, and against the standard human design methodology, the acceleration is higher than 20 times. The methodology enables on-the-fly power/area optimization of all operational transconductance amplifiers in sixth-order tunable vowel filters without need for re-design.

An integrated digital controller design for dc-dc converter is proposed in this paper. The proposal presents a multiple- band dual-stage (MBDS) delay line A/D converter (ADC) for wide dynamic range of operation with reduced ripple, chip area, and power consumption. This proposal also introduces a novel folding logic for digital error calculation and dual-mode error control PID for improving transient response. A complete closed-loop experimental prototype is demonstrated on a field-programmable-gate- array-based setup. The feasibility and functionality of the proposed digital controller is verified with a closed-loop synchronous buck converter prototype that switches at 1 MHz and regulates over a wide output voltage range of 1.6-3.3 V. The proposed MBDS delay line ADC is fabricated with discrete logic gates and flip-flops. The integrated digital controller is also implemented using standard cell-based design methodology in 0.5-mum CMOS technology. The design reduces 33 % on-chip area compared to an equivalent of 64 tap delay line ADC. The complete digital controller chip takes less than 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon area and consumes an average current of 92 muA at 1-MHz switching frequency. The voltage-mode digital loop achieves tracking time of less than 10 mus for 1-V step change of the reference voltage and settling time of 20 mus. Post layout simulation and experimental results are demonstrated.

Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.