A TCAM-based Caching Architecture Framework for Packet Classification

Packet classification based on rules of packet header fields is the key technology for enabling software-defined networking (SDN). Ternary content addressable memory (TCAM) is a widely used hardware for packet classification; however, commercially available TCAM chips have only limited storage. As the number of supported header fields in SDN increases, the number of supported rules in a TCAM chip is reduced. In this work, we present a novel scheme to enable packet classification using TCAM with entries that are narrower than rules by storing the most representative field of a ruleset in TCAM. Due to the fact that not all rules can be distinguished using one field, our scheme employs a TCAM-based multimatch packet classification technique to ensure correctness. We further develop approaches to reduce redundant TCAM accesses for multimatch packet classification. Although our scheme requires additional TCAM accesses, it supports packet classification upon long rules with narrow TCAM entries, and drastically reduces the required TCAM storage. Our experimental results show that our scheme requires a moderate number of additional TCAM accesses and consumes much less storage compared to the basic TCAM-based packet classification. Thus, it can provide the required scalability for long rules required by potential applications of SDN.

Using packet classifier algorithms in packet processing network systems is the key idea to process packets rapidly. These algorithms are so important, especially in processor equipments used in internet backbones. Ternary content addressable memories (TCAM) are used to do parallel search in hardware implementation of these algorithms. Despite the accessibility of high-speed search, one of main problems to use TCAM is its high consumption power supply. In this study, a new technique is provided to reduce memory consumption in TCAM blocks which are used in hardware classifier. In classifier architecture, first, decision tree is created and classifier rules are distributed among its leaf nodes. Since each leaf of the tree corresponds to one TCAM block, rules are included in different blocks of TCAM corresponding to tree structure, in the second stage. In this architecture, a supplementary TCAM block is used as the general block. Recent architectures have encountered memory waste and a considerable increase in power consumption due to unbalanced distribution of rules in main TCAM blocks and unexpected increase in the number of repeated rules in the general block. In this study, a new algorithm is offered to optimize rule distribution in TCAM blocks in the first stage of packet classification. Efficiency of the proposed architecture which uses intelligent cuts has been compared with recent architectures. Comparing results shows that the proposed method can distribute rules in TCAM block more balanced than competitor architectures and at the same time, reduce the number of rules assigned to the general TCAM block.

Network packet classification is a key functionality provided by modern routers enabling many new network applications such as quality of service, access control and differentiated services. Using ternary content addressable memories (TCAMs) to perform high-speed packet classification has become the de facto standard in industry. However, despite their high speed, one major drawback of TCAMs is their high power consumption. Although SmartPC, the state-of-the-art technique, was proposed to reduce power consumption by constructing a pre-classifier to activate TCAM blocks selectively, its bottom-up approach restricts its ability of grouping rules into disjoint TCAM blocks. In this paper, we propose a top-down approach for two-stage TCAM-based packet classification. The novelty of our work is the intelligent combination of software-based packet classification with TCAM-based techniques. We start by constructing a set of decision-trees for the packet classification rules, which enable the subsequent steps an excellent global view on the relationships among rules. The decision-trees are then mapped to TCAM blocks with flexible heuristics. Our top-down framework addresses the bottlenecks (the number of general rules, which have to be activated unconditionally every time) of SmartPC very effectively. Using ClassBench in our experimentations, we show that our technique is able to restrict the number of general rules to just 1% of the overall rule set. This leads to a dramatic power reduction of up to 98%, and 96% on average, which significantly outperforms SmartPC.

The speed requirement for the routing table lookup and the packet classification is rapidly increasing due to the increase in the number of packets needed to be processed per second. The hardware-based packet classification relies on ternary content addressable memory (TCAM) to meet this speed requirement. However, TCAM consumes huge power and also supports only for longest prefix match and exact match, where the classification rule also has a range match (RM) field. Hence, it is mandatory to encode the RM into prefix match to accommodate the rule in TCAM. In the worst case, one rule is encoded into (2 W -2) 2 rules (where W is a number of bits to represent range). This work proposes a novel RM architecture, and a detailed analysis about the range field on the standard dataset and the real-life classifier rules are presented. In the literature, the existing RM architecture is used to avoid the range to prefix conversion, but due to the serial operation, it lacks in performance. For constant time lookup, TCAM is the best option, but it does not support RM. The proposed architecture takes one clock cycle for RM and does not require any encoding/ conversion. Hence, there will be a single entry for every rule. It is observed that just 4% of the two-dimensional range rules are present in this dataset, and it will increase the rule set size by 4 times in the best case and nearly 30 times in the worst case. The proposed RM circuit is operated in parallel with TCAM without compromising the speed, and this circuit saves huge power around 70% and area around 61%, where the range to prefix conversion/encoding is completely avoided. The proposed architecture is well suited for current IPv4- and IPv6-based networks, as well as in software-defined networks in the near future.

Ternary Content Addressable Memory (TCAM) is the de-facto standard device used for high-speed packet classification. Despite its capability for line-speed queries, it is very power hungry and area inefficient The latest TCAM devices by leading vendors come with an power saving mechanism where a subset of its TCAM blocks can be selectively activated. Recent research efforts exploit this feature to reduce power consumption with pre-classification steps. However, the state-of-the-art technique achieves power savings at the expense of poor utilization of TCAM capacity, and the potential of power reduction is not fully exploited in many cases. In this paper, we propose GreenTCAM, an optimized two-stage design for TCAM-based packet classification. Based on common characteristics of rule sets, our design is able to group rules more compactly into TCAM blocks, and activates a minimum subset of these blocks for each incoming packet. Experimental results show that our design achieves a 93.6% power reduction with a TCAM storage overhead of only 5.6% on average.

Ternary content addressable memory (TCAM) is a key component in various digital systems due to its fast lookup operation. Symmetric and asymmetric TCAM cells are two widely used cells for implementing a TCAM array. This paper presents several comparison fault models of TCAMs with asymmetric cells based on electrical defects. Some new comparison faults which do not exist in a TCAM with symmetric cells are found. One march-like test algorithm TAC-H is also proposed to cover the defined comparison faults. The TAC-H consists of 8N Write operations and (3N + 2B) Compare operations for an N × B-bit TCAM with Hit output only. We also propose two march-like diagnosis algorithms to identify the defined comparison faults of TCAMs with asymmetric cells. The first diagnosis algorithm DAC-H requires 5N Write operations, 3N Erase operations, and (5N + 2B) Compare operations to distinguish 100 percent comparison faults for a TCAM with Hit output only. The second diagnosis algorithm DAC-P requires 3N Write operations, 1N Erase operations, and (5N + 2B) Compare operations to distinguish 100 percent comparison faults for a TCAM with Hit and priority address encoder outputs.

Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing designs support only a small TCAM size even with large FPGA devices. They also suffer from significant throughput degradation in implementing a large TCAM, mainly caused by deep priority encoding. This paper presents a scalable random access memory (RAM)-based TCAM architecture aiming for efficient implementation on state-of-the-art FPGAs. We give a formal study on RAM-based TCAM to unveil the ideas and the algorithms behind it. To conquer the timing challenge, we propose a modular architecture consisting of arrays of small-size RAM-based TCAM units. After decoupling the update logic from each unit, the modular architecture allows us to share each update engine among multiple units. This leads to resource saving. The capability of explicit range matching is also offered to avoid range-to-ternary conversion for search functions that require range matching. Implementation on a Xilinx Virtex 7 FPGA shows that our design can support a large TCAM of up to 2.4 Mbits while sustaining high throughput of 150 million packets per second. The resource usage scales linearly with the TCAM size. The architecture is configurable, allowing various performance trade-offs to be exploited. To the best of our knowledge, this is the first FPGA design that implements a TCAM larger than 1 Mbits.

Memory which is used for searching applications, like Network routers, operating at a higher speed is called Ternary Content Addressable Memory (TCAM). The requirement of TCAM is gradually growing in the searching field applications. TCAM memories are usually built in ASIC (Application Specific Integrated Circuit) which offers searching operation at a higher speed in a predetermined time but is expensive in cost. TCAMs designed on FPGAs (Field Programmable Gate Array) experience high power consumption, larger use of FPGA resources, and suffer from the inefficiency of storage. TCAM using multipumping and multiported SRAM is designed for achieving an effectual use of FPGA resources, and a reduction in usage of power and area. In the present SRAM based TCAM designs, there is an exponential growth in memory usage due to the increase in the patterns of TCAM, which is reduced by cascading the multiple blocks of SRAM (BRAMs) in FPGA that makes growth linear. BRAMs of FPGAs have restrictions in depth, which restricts the effectual storage of TCAM bits. In this paper, a modified TCAM design is proposed which avoids this restriction by using shallow sub-blocking of BRAMs. The design proposed in this paper operates the multiported SRAM by using the dual-port BRAM and by clocking it internally at a higher frequency using multipumping technique which allows access of the BRAM subblocks in one cycle of the system clock. These modifications in the divisional traditional TCAM table results in an effectual design of TCAM memory. The proposed design is coded in Verilog and simulated using the Xilinx ISE tool and was implemented on a Virtex 7xc7vx485 FPGA device. The proposed design has better performance, in terms of 26% reduction in power and 7% reduction in area, as compared to existing SRAM based TCAM design.

Ternary Content Addressable memory (TCAM) is widely used in wireless net, image processing, data compression, etc. where high-speed data search is required. Despite using faster matching algorithms, software search remains much slower than TCAM based hardware searches. In this paper, we propose a high-speed 11 transistors (11-T) TCAM with significant improvement in speed and power compared to the existing 18-T TCAM and 9-T quasi-static TCAM. Results have been verified via Spice simulations performed using UMC 28-nm technology for a $16 \times 16$ TCAM array. Results show that the proposed 11-T TCAM is 21% and 10$\times$ faster than its counterpart 9-T and 18-T TCAM respectively. The proposed 11-T TCAM consumes 30% and 1.5 % less energy for a word search operation in a $6 \times 16$ array compared to the existing 9-T TCAM and 18-T TCAM respectively.

Ternary content addressable memory (TCAM) are widely used for their high speed search operation. However, TCAMs have larger area and power consumption. The use of advanced technology nodes and emerging non-volatile devices can improve the same. In this paper, magnetic tunnel junction (MTJ), which is a non-volatile device is used to reduces the overall power consumption of TCAM by realizing zero standby power. A novel Verilog-A model of MTJ which is suitable for SOI technology was developed. The conventional NOR and NAND type TCAM cells, and two MTJ based hybrid TCAM cells are constructed using 45 nm RF-SOI technology node. The proposed cells use only one transistor for precharge. The simulation results show that the NOR and NAND type TCAM cells consumes 29.11 μW and 19.33 μW of power respectively. The MTJ based TCAM cells consume 7.33 μW and 8.58 μW of power which is about 70% and 63% lower compared to the NAND and NOR TCAM cells.

With the increasing internet service complexity, providing secured quality service has become a major concern. In the earlier systems, data was believed to be safer on internet without being intercepted. Now these internet vulnerabilities cannot be ignored as these weaknesses are used by many to carry out malicious activities. In order to tackle these problems, internet service providers are trying to find better options. One such technique gaining popularity in the recent decade is Deep Packet Inspection (DPI), which can be provided using software or hardware methods. It is reported that hardware is providing better solution than software. In this review article, we have introduced one such hardware, Ternary Content Addressable Memory (TCAM), which could perform complete packet inspection (packet header and payload inspection). In the first section, we have focused on evolution of packet filtering system. Later the discussion is divided into two parts: (i) packet classification using TCAM, and (ii) payload inspection (pattern matching and regular expression) using TCAM.

Memory-based computing using associative memory has emerged as a promising solution to reduce the energy consumption of important classes of streaming applications such as multimedia by avoiding redundant computations. In associative memory, a set of frequent patterns that represent basic functions are pre-stored in ternary content addressable memory (TCAM) and reused. The primary limitation to using associative memory in modern parallel processors is the large search energy required by TCAMs. In TCAMs, all match rows, except hit rows, precharge and discharge in every search operation, resulting in high and undesirable energy consumption. In this paper, we propose a new multiple-access single-charge (MASC) TCAM architecture which is capable of searching TCAM contents multiple times with a single precharging cycle. In contrast to previous designs, the MASC TCAM keeps the match-line voltage of all miss-rows high and uses their charge for the next search operation, while only the hit rows discharge. We use a periodic refresh scheme to guarantee the accuracy of the search. We also implement a new type of approximate associative memory by setting longer refresh times for MASC TCAMs, which yields search results within 1–2 bit Hamming distances of the exact result. Our evaluation on AMD Southern Island GPU shows that using MASC associative memory can improve the average GPGPU energy efficiency by 36.6%, 40.2% and 39.4% for exact matching, selective 1-HD and 2-HD approximations respectively, with acceptable quality of service (PSNR>30dB). These energy savings are 1.8X and 1.6X higher than GPGPU using exact matching TCAM and approximation TCAM that uses voltage overscaling, respectively.

Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper shows a novel way in generating keys to cover the correct match. It proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don’t-care keys (X-keys). First, this paper observes the case of single-bit-flip errors by X-TCAM. Second, it extends the X-TCAM to the case of multiple-bit-flip errors called KX-TCAM, where K stands for the maximum number of errors ${k}$ . KX-TCAM corrects up to ${k}$ -bit-flip errors and enhances the tolerance of the TCAM against soft errors, where ${k}$ is the maximum number of bit flips in a word of a TCAM. KX-TCAM consists of a TCAM, a preprocessed don’t-care-bit index look-up memory (X look-up), and a backup error checking and correction (ECC)-SRAM. First, KX-TCAM randomly selects a search key. After that, KX-TCAM detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and KX-TCAM refreshes the TCAM words by using the backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of KX-TCAM significantly outperforms existing state-of-the-art schemes. Moreover, the hardware overhead of KX-TCAM is small due to the use of a single TCAM. KX-TCAM can be easily implemented and is useful for fault-tolerant packet classifiers.

Ternary content addressable memory (TCAM) is used for high-speed table lookups. The dynamic power consumption of TCAMs is one of the main challenges for keeping up with high performance requirements. System level reliability is impacted by devices that produces large peak current demands on the power grid. This paper presents a TCAM compiler based on a static complementary TCAM bitcell for reduced dynamic power and reduced decoupling capacitance(dcap) requirement. The two stage architecture comprise of static TCAM cells with a match forward feature and then a static AND-tree structure. This TCAM compiler configurations have been implemented on 40nm CMOS technology testchip and experimental results demonstrate the performance upto 650Mhz and 0.5fJ/bit/search energy for a 512wordsx256bit macro.

Ternary Content Addressable Memories (TCAMs) have become the de facto standard in industry for fast packet classification. Unfortunately, TCAMs have limitations of small capacity, high power consumption, high heat generation, and high cost. The well-known range expansion problem exacerbates these limitations as each classifier rule typically has to be converted to multiple TCAM rules. One method for coping with these limitations is to use compression schemes to reduce the number of TCAM rules required to represent a classifier. Unfortunately, all existing compression schemes only produce prefix classifiers. Thus, they all miss the compression opportunities created by non-prefix ternary classifiers.