A Thought-Operated Digital Random-Access Memory.

In the rapidly evolving landscape of modern electronics, memory devices and circuits play a pivotal role in determining system performance, energy efficiency, and scalability. Traditional memory technologies, such as Dynamic Random Access Memory (DRAM) and NAND flash, face challenges related to scaling limits, latency, power consumption, and endurance, particularly as demands for faster and more efficient data storage grow. Emerging non-volatile memory (NVM) technologies like Resistive Random Access Memory (ReRAM), Phase-Change Memory (PCM), and Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) offer potential solutions to these challenges, but their combination into existing systems poses design and manufacturing hurdles. The primary problem lies in balancing storage performance with power efficiency while ensuring scalability for advanced applications such as artificial intelligence (AI), Internet of Things (IoT), and high-performance computing (HPC). Innovations in circuit design, including advanced error-correction mechanisms, adaptive voltage scaling, and low-power architectures, are critical in enhancing the overall performance of memory systems. This study employs a hybrid approach, combining novel circuit design techniques with the combination of emerging NVM technologies. Simulations were performed to evaluate the performance metrics, including write latency, energy consumption, and endurance. Results show that ReRAM-based memory designs achieved a 35% reduction in write latency and a 50% improvement in energy efficiency compared to traditional DRAM, while PCM demonstrated superior endurance with up to 10^8 write cycles. Furthermore, STT-MRAM circuits showed promise with a 40% reduction in standby power consumption. These advancements in memory circuits and devices highlight the potential for significant improvements in storage performance and efficiency, addressing the growing needs of modern electronic systems and paving the way for future innovations in computing.

Herein, the supercritical hydrogen treatment is proposed to improve the performance of zinc oxide‐based resistive random access memory. After treatment, the treated device not only achieves the forming‐free characteristic but also gets enhanced in its memory window, reset voltage, and reliability. Moreover, X‐Ray photoelectron spectroscopy analysis confirms the forming‐free characteristic of the treated device since the treatment decreases the concentration of ZnO bonding in the zinc oxide thin film, leading the conductive filament to be constructed in the zinc oxide switching layer. Next, the carrier transport mechanism is investigated by fitting current–voltage curves. Finally, the physical models based on the electrical properties and the material analyses are introduced to illustrate the oxygen ions and hydroxide ions that create the forming‐free characteristic and better memory characteristics in the random access memory device after the supercritical fluid treatment. Hence, this method demonstrates the promising practical and effective utilization of enhancing memory devices, in the future.

A beamformer for an ultrasound imaging system is provided, the ultrasound imaging system having a probe having a transducer array for transmitting and receiving analog signals, and a personal computer. The beamformer includes a beamformer software application module configured for execution by the computing device for performing at least partial beamforming processing on digital data transmitted between the transducer array and the computing device, and means for exchanging signals and data between the transducer array and the computing device and performing at least one of A/D and D/A conversions on the exchanged signals and data. In the preferred embodiment, the beamformer further includes a module integrated within architecture of the computing device, wherein the integrated module is preferably Random Access Memory (RAM) included in storage means of the computing device. A method is further provided for performing a transmit beamforming process in an ultrasound system having a computing device and a probe including a transducer array, the method including the steps of performing transmit beamforming processing in the computing device in accordance with transmit settings to generate digital transmit data, storing the digital transmit in the data storage memory, retrieving the digital transmit data from the storage memory, converting the digital transmit data to analog transmit signals, and transmitting the analog transmit signals to the transducer array. A method is further provided for performing a receive beamforming process in an ultrasound system having a computing device including storage memory, an interface module and a probe including a transducer array, the method including the steps of receiving analog signals from the transducer array, converting the analog signals to digital data, storing the digital data in the storage memory, retrieving the digital data from the storage memory, and performing receive beamforming operations on the digital data by the computing device.

Garbage-collected language runtimes carefully tune heap limits to reduce garbage collection time and memory usage. However, there's a trade-off: a lower heap limit reduces memory use but increases garbage collection time. Classic methods for setting heap limits include manually tuned heap limits and multiple-of-live-size rules of thumb, but it is not clear when one rule is better than another or how to compare them. We address this problem with a new framework where heap limits are set for multiple heaps at once. Our key insight is that every heap limit rule induces a particular allocation of memory across multiple processes, and this allocation can be sub-optimal. We use our framework to derive an optimal "square-root" heap limit rule, which minimizes total memory usage for any amount of total garbage collection time. Paradoxically, the square-root heap limit rule achieves this coordination without communication: it allocates memory optimally across multiple heaps without requiring any communication between those heaps. To demonstrate that this heap limit rule is effective, we prototype it for V8, the JavaScript runtime used in Google Chrome, Microsoft Edge, and other browsers, as well as in server-side frameworks like node.js and Deno. On real-world web pages, our prototype achieves reductions of approximately 16.0% of memory usage while keeping garbage collection time constant. On memory-intensive benchmarks, reductions of up to 30.0% of garbage collection time are possible with no change in total memory usage.

Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the target applications, these systems will also have custom memory and bus architectures. Because of performance and cost constraints, these systems must be carefully designed to balance system partitioning and resource sharing. The sheer size of the design space requires that tools be able to do this balancing. We have developed an augmented simulated annealing synthesis tool that uses system performance and layout evaluation to drive simultaneous data mapping, memory allocation and bus synthesis. Exploring these optimizations at the same time, our approach reverses traditional techniques and determines bus topology first rather than last, thereby exposing a larger design space and taking advantage of cost-saving resource sharing unavailable to previous approaches that allocate memories first. This results in 20% cost reduction for high-performance designs as well as 27% for low-cost designs in comparison with an approach that performs memory allocation and data mapping separately from bus synthesis.

Perpendicular spin-transfer-torque magnetic random access memory (p-STT-MRAM) is a promising candidate memory device for replacing dynamic random access memory (DRAM) facing with 10-nm sub scaling down. In addition to scaling down, p-STT MRAM has many advantages like fast write/read speed (~10ns) as DRAM, low power consumption (<1pJ), high endurance (>1014), and non-volatility (retention time > 10 years). But to replace DRAM, there are several challenges to be solved. First, high tunneling magneto-resistance (TMR) ratio for read sensing margin. Second, low critical current density(J C) for low power consumption. Third, thermal stability(Δ) for long retention time to save data. And also these parameters should be achieved at 350oC annealing temperature of the back-end-of line (BEOL) to be commercialized. Among them, thermal stability is closely related with cell size. As a cell size of MTJ decreases to achieve a high density memory device, thermal stability decreases with retention time, thus it is not easy to implement both high density and non-volatile memory device simultaneously by decreasing the cell size of MTJ. In our study to solve this issue, we propose the p-STT multi-level cell (MLC) magnetic tunnel junction (MTJ) because MLC MTJ can satisfy both high density and non-volatile memory device at the same time. In particular, we design the MTJ structure with dual free layers and MgO tunnel barriers, so that the MTJ can demonstrate four resistance states. In addition, we investigated the effect of the thickness of two free layers and MgO tunnel barriers on two magneto-resistance (MR) and switching voltage. In our experiments, the p-STT MTJ spin-valves were fabricated on 12-inch-diameter Si/ SiO2/W/TiN wafers by utilizing a 12-in. multi-chamber-cluster magnetron-sputtering system under a high vacuum (less than 110-8 Torr) without breaking the vacuum. Then, all samples were subject to ex-situ annealing at 350℃ at a back end of line (BEOL) for 30 minutes under a magnetic field of 3 tesla. In our presentation, we present how to optimize the thicknesses of two free layers and MgO tunnel barriers. In addition, we repot how the magnetic behavior and the resistance of MTJ is affected by magnetic and how the magneto-resistance of MTJ is closely related to the crystallinity of two MgO tunnel barriers. Acknowledgements This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2017R1A2A1A05001285)

Increasing evidence points to the importance of dendritic spines in the formation and allocation of memories, and alterations of spine number and physiology are associated to memory and cognitive disorders. Modifications of the activity of subsets of synapses are believed to be crucial for memory establishment. However, the development of a method to directly test this hypothesis, by selectively controlling the activity of potentiated spines, is currently lagging. Here we introduce a hybrid RNA/protein approach to regulate the expression of a light-sensitive membrane channel at activated synapses, enabling selective tagging of potentiated spines following the encoding of a novel context in the hippocampus. This approach can be used to map potentiated synapses in the brain and will make it possible to re-activate the neuron only at previously activated synapses, extending current neuron-tagging technologies in the investigation of memory processes.

Swarm robotics is an emerging field capable of accomplishing complex tasks through collective behaviour. However, it continues to face persistent challenges in secure communication, decentralized decision-making, and scalability. To operate effectively in resource-constrained environments, swarm networks require a decentralized mechanism that is secure, fast, and efficient. Although many studies have explored the use of blockchain technology for swarm robotics, existing blockchain consensus algorithms such as Proof of Work (PoW), Proof of Stake (PoS), and their variants remain unsuitable due to high computational complexity and risk of stake centralization. To address these challenges, we introduce the blockchain-based Rotational Leadership Role (RLR) consensus algorithm, a voting-based consensus re-engineered from the Raft approach, together with Decentralized Task Authorization and Validation (DeTAV), a token-based mechanism for context-aware task validation. This design ensures efficiency, security, and scalability in swarm robotics and drone systems. RLR is lightweight and well suited to operate within the limited computing resources of small robots or aerial drones. To validate its performance, a custom-built robotic simulator was developed as part of this research. Experiments conducted with up to 70 concurrent robots demonstrated that RLR consumed under 90 MB Random Access Memory (RAM) and 12% Central Processing Unit (CPU), whereas PoW required 460 MB RAM and 27% CPU with a minimum difficulty level of 21, reflecting an 80% reduction in memory usage and a 55% reduction in CPU consumption. Scalability tests with 4 to 70 robots further revealed RLR’s scalability with an average of 78% higher throughput, 47% lower election latency, and 34% lower consensus latency. Additionally, under the simulated attack scenarios and assuming uncompromised cryptographic keys, DeTAV’s context-based validation consistently achieved 100% success in detecting and isolating Byzantine nodes, while reducing Quality of Detection (QoD) time by 67%. Collectively, these results confirm that RLR with DeTAV effectively meets the efficiency, security, and scalability requirements of swarm robotic and drone networks.

This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.

The performance of memory allocation operations significantly impacts the global performance in most computing applications. Thus, the choice of a memory allocator is an important aspect when projecting more sophisticated computing systems. The strong correlation between the dynamic memory use profile and the allocator performance requires the allocator to be chosen through an experimental study. This research carried out an exploratory study on a set of six widely used memory allocators: Ptmalloc2 (standard glibc allocator), Ptmalloc3, Hoard, Miser, TCMalloc, and Jemalloc. The workloads used to evaluate the allocators were based on a characterization study on memory use of seven application, two of which for servers and five for desktops. Each allocator was evaluated regarding its response time and memory usage in a set with 648 different execution scenarios. The results showed that the allocators with the shortest mean execution time also made the best use of parallelism in scenarios with more than one thread and one processor. The allocators Jemalloc and TCMalloc were, on average, five times faster than the standard glibc allocator. Under certain conditions, the allocator Hoard provided substantial memory savings of up to 75% when compared with the other allocators assessed. These results emphasize the importance of allocator choice when projecting applications in face of the significant differences observed experimentally in this study.

Document stores have become one of the key NoSQL storage solutions. They have been widely adopted in different domains due to their ability to store semi-structured data and expressive query capabilities. However, implementations differ in terms of concrete data storage and retrieval. Unfortunately, a standard framework for data and query optimization for document stores is nonexistent, and only implementation-specific design and query guidelines are used. Hence, the goal of this work is to aid automating the data design for document stores based on query costs instead of generic design rules. For this, we define a generic storage and query cost model based on disk access and memory allocation that allows estimating the impact of design decisions. Since all document stores carry out data operations in memory, we first estimate the memory usage by considering characteristics of the stored documents, their access patterns, and memory management algorithms. Then, using this estimation and metadata storage size, we introduce a cost model for random access queries. We validate our work on two well-known document store implementations: MongoDB and Couchbase. The results show that the memory usage estimates have the average precision of 91% and predicted costs are highly correlated to the actual execution times. During this work, we have managed to suggest several improvements to document storage systems. Thus, this cost model also contributes to identifying discordance between document store implementations and their theoretical expectations.

HEART SOUNDS CHARACTERISTICS FROM A 3D ACCELEROMETER IN HEART FAILURE PATIENTS

: Extensive electrical characterizations were performed on 256K bit and 512K bit ultra violet erasable PROMs (UVEPROMs), 64K bit electrically erasable PROMs (EEPROMs), 64K static RAMs (organized as 8Kx8 bits), 256K dynamic RAMs (CMOS) and 32R16 PAL devices available from the merchant semiconductor industry. Based on the data obtained from the devices, parameter limits were established and proposed for the draft MIL-M-38510/XXX specifications. The data, proposed limits and test methodologies and the related discussions are presented. Keywords: Memory devices; Random access memories; Monolithic structures; Semiconductors; Complementary metal oxide semiconductors.

Phase‐change random access memory (PCRAM) is a leading candidate for emerging nonvolatile memory devices due to its fast switching speed, scalability, and complementary metal‐oxide‐semiconductor (CMOS) compatibility. However, traditional PCRAM relies on amorphous‐to‐crystalline switching, which suffers from high energy requirements and reliability issues. To address these challenges, in this study, the crystalline polymorphic phase‐change behavior as an alternative, which eliminates reliance on the amorphous phase and its associated limitations, is investigated. Herein, the transition‐metal tellurides, specifically a VTe binary system, are focused on and their potential for polymorphic phase transitions is investigated, leveraging insights from the crystalline polymorphic switching's dynamics of MnTe melting free phase‐change material. The binary phase diagram of VTe suggests that the polymorphic transition between the V3Te4 and V5Te8 phases can be obtained in the composition of V:Te ≈ 0.4:0.6. In this study, a VTe thin film is deposited and its polymorphic transition properties are investigated. The associated electrical and optical property changes are also analyzed. Finally, a VTe‐based memory device is fabricated and tested.

Versatile zirconium oxide as a ceramic has propelled a rapid development of science and technology for diverse applications. Among the class of ceramics it holds a distinctive position due to its excellent physical, chemical and mechanical properties owing to its phase transformation. Zirconia is high k- dielectric, mechanical resistance and high radiation tolerance material. Although, this material replace SiO2 due to its higher dielecotric constant so it can be employed to various memory device applications. It has essential implications in nuclear reactors, inert matrix fuel, nuclear waste systems, container for radioactive materials and designing of new materials owing to its high radiation tolerance property. Dentists proclaim zirconium oxide “ceramic steel” where it has attracted prosthetic dentistry because of its strength and esthetics are admired. Addition of few percentages of stabilizers such as Y2O3, MgO and Ni etc. make it useful for specific applications. Zirconium oxide ceramic is indispensably used as an electrode and electrolyte in energy efficient solid state electrochemical devices (fuel cells) that generates electricity with good efficiency from natural gas and fuel cell plants and provides auxiliary power in vehicles. One of its important phase transformation mechanism is being focused and extensively reviewed due to the effect of temperature variation and ion beam irradiation effect.The objective of current review is to present the knowledge of extensive properties, synthesis techniques and its various implicationsand guidelines for optical, medical, fuel cells, biological and electrical and memory devices and nuclear applications. The advantages of zirconia with respect to other oxide materials are also reviewed.