A tunable, power efficient active inductor-based 20 Gb/s CTLE in SerDes for 5G applications

A 5–30 Gb/s receiver analog front-end (AFE) cascading transimpedance amplifier (TIA) and continuous-time linear equalizer (CTLE) were implemented using a Taiwan Semiconductor 180 nm process. The system comprises a two-stage differential input pair CTLE, TIA, and a differential termination resistor Rm. A source-degenerated transconductance stage was adopted in the CTLE, and source follower and shunt feedback resistor stages were adopted in the TIA. The proposed CTLE could achieve high frequencies by altering the tail current with fixed degenerate capacitance CS and resistance RS. The proposed AFE achieved high bandwidth, and the use of a feedback resistor Rf and inductor Lf improved its high-frequency performance. Simulation results revealed that the CTLE can compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open closed eyes in a 6 Gb/s non-return-to-zero signal with a bit error rate of 0.16 × 10−12 for a 231 − 1 pseudorandom binary sequence input. The AFE could compensate for 12 dB of channel loss at a 15 GHz Nyquist frequency and can open closed eyes in a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power at 1.8 V.

An alternating current (ac)-coupled high-speed receiver analog front end is capable of shifting the input direct current (dc) level without extra current consumption and signal degradation at high frequencies. However, the dc wander due to the high-pass characteristic of the ac-coupled front end may degrade the receiver performance because it equivalently modulates the sampling threshold voltage of the sampler. While this modulation may be negligible for highly dc-balanced input, it shows observable degradation in Peripheral Component Interconnect Express (PCIe) 3.0 receivers operating at 8 Gb/s. In addition, analog equalization is generally required for a PCIe 3.0 receiver front end. This paper presents techniques to add linear equalization and dc wander compensation into an ac-coupled receiver front end. The proposed linear equalization scheme attenuates the low-frequency energy and keeps the high-frequency energy. The proposed dc wander-compensation method is independent of process, voltage, and temperature; therefore, there is no need for calibration or compensation. The proposed schemes have very low power consumption and very good linearity because only passive and linear components are utilized in the main signal path. The proposed schemes were confirmed by simulation.

This paper presents a 20 Gb/s receive equalizer including an adaptive continuous time linear equalizer (CTLE) and a 2-tap half-rate decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE can adjust the ratio of high frequency and low frequency components adaptively by detecting the energy at both ends of a slicer and then generating a control signal by an integrator. Following the CTLE is a half-rate DFE which can get a better trade-off between the working speed and design complexity especially for the case of 20 Gb/s or above. The chip area including pads and chip guarding is about 0.72 × 0.86 mm2 and the power consumption is about 528 mW. Post simulation results show that the horizontal eye opening of the equalized data can be up to 0.9 UI at 20 Gb/s.

As the data rate has been increased over 10 Gb/s with copper interconnect, the intersymbol interference (ISI) caused from the channel loss should be compensated. While a decision feedback equalizer (DFE), which is widely used in the receiver can compensate the ISI, its ability to enhance the signal-to-noise ratio (SNR) is limited especially for high frequency data patterns (alternating data patterns). Even a DFE with a large number of taps, which has powerful compensation capacity for ISI, can improve only limited amount of SNR. To improve SNR, this brief presents a 1/4th baud-rate continuous-time linear equalizer (CTLE) and a two-tap DFE. The 1/4th baud-rate CTLE recovers data to be adequate for the DFE, and remaining ISI is removed by the DFE. To boost the high frequency gain of the DFE, exclusive or merged adders are introduced, so the proposed equalizer is more tolerant against channel noise. It compensates 21.7-dB channel loss and operates with 11.5-Gb/s data rate as it consumes 25.35 mW from 1.3 V supply in a 110-nm CMOS technology.

Active CMOS inductors have emerged as essential components in modern integrated circuits (ICs), offering significant advantages over passive inductors in terms of size, performance, and power efficiency. This paper provides a comprehensive overview of the design methodologies, key design metrics, and applications of active CMOS inductors. This paper begins with introducing fundamental concepts of inductors in CMOS technology, highlighting the limitations of passive inductors and the evolution of active inductors. After that, it discusses the benefits and limitations of several design approaches, including bootstrapped, negative resistance-based, LC resonator-based and gyrator C-based active inductors. Furthermore, it examines the key design considerations crucial for achieving desired performance metrics such as equivalent inductance, quality factor (Q-factor), self-resonant frequency, power consumption, noise performance, tunability, linearity, and bandwidth. It also outlines future research directions and emerging trends in active CMOS inductor design, paving the way for continued innovation and advancement in this field.

In this work, the low power receiver front-end is investigated in the 865-867 MHz unlicensed band. The low noise amplifier (LNA), Mixer, local oscillator and active filter are integrated to investigate the overall performance of receiver front-end. The individual components are studied to optimize the power consumption without degrading the overall performance of receiver frontend. From the results it can be seen that for optimal power of 18mW, 2.01 dB of noise figure was attained. For integrated LNA with mixer, at optimal 48mW power, noise figure was found to be 2.84 dB. The balun circuit in the receiver was replaced by a current amplifier and performance was compared. Receiver front-end for 865-867 MHz at 60mW power with 3.3dB noise figure was obtained.

This work presents a self-adaptation algorithm to automatically adjust the peaking settings of a continuous-time linear equalizer (CTLE) in a high-speed PAM4 receiver. A statistical approach is adopted to improve the robustness and flexibility of the adaptation algorithm. The PAM4 top level distribution around the peak value of several consecutive top levels guides the CTLE to attain the optimal digital settings. By performing the peak detection at the output of the equalization summer, the effect of digital equalization is inherently accounted for by the proposed algorithm. To demonstrate the effectiveness of the proposed algorithm, a PAM4 receiver employing two stages of CTLE and 1-tap feed forward equalizer (FFE) is designed to compensate up to 11.8-dB channel loss for a data rate of 56 Gb/s.

This work proposes a RX front-end structure, which is used for channel equalization of 25Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005mm2 designed in 65nm CMOS, the power consumption of which is 96mW under 1.2V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35dB at 12.5GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171mV and 0.61UI at the BER of 10-12, respectively.

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20”, 30”, 40” FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a 0.13 μm process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3,4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.

The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive equalization system with optimized eye-opening monitor is proposed. The designed eye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm, and the eye diagram is obtained by undersampling with the low-speed asynchronous clock. With the eye-opening monitor into the adaptive loop, an adaptive equalization system combined with continuous-time linear equalization (CTLE) is completed. And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. And postsimulation results show that it can offer compensation from 6 to 21 dB for 1.25–12.5 Gbps range of receiving data, which achieves a large range of data rate and channel loss, and its power efficiency is 0.046 pJ/bit/dB for the worst case, which is better than most previous works.

In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign-sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth- and fifth-post-cursors is used as an indicator for CTLE adaptation, and the validity is substantiated by numerical analysis and simulation. Furthermore, the concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI). The proposed dLev is acquired by simply adjusting up and down ratios of the dLev update equation. The prototype test chip is implemented in 65-nm CMOS technology and occupies an active area of 0.174 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The proposed adaptive equalizers compensate for the channel loss of up to 34 dB at 10.8 Gb/s. Total power consumption of the receiver is 37.2 mW at 10.8 Gb/s, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.1 pJ/b/dB is achieved.

This paper presents a digitally controlled 1-V 30-Gb/s 1.37-pJ/b optical receiver in 65-nm CMOS technology. This receiver consists of an inverter-based inductive transimpedance amplifier, a fully integrated low-dropout regulator, a main amplifier, a three-stage-cascaded continuous-time linear equalizer (CTLE), a two-stage limiting amplifier, and an output driver. The CTLE consists of three cascaded stages with different peaking frequencies (5, 12, and 20 GHz) offering 16 dB of adjustable low-frequency gain to accommodate different photodetector (PD) characteristics. The electrical measurements demonstrate a maximum transimpedance gain of 83 dBΩ (14,125 Ω), an output swing of 300 mV, a -3-dB bandwidth of 24 GHz, and a power consumption of 41 mW. Moreover, optical measurement results with a 28-Gb/s PD show that the receiver achieves 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> BER at 30 Gb/s for a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> -1 PRBS input with a -5.6-dBm input sensitivity. Using a lower bandwidth 14-Gb/s PD, the receiver can still reach 30 Gb/s at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> BER with only a 0.6-dB degradation in input sensitivity, demonstrating the effectiveness of the proposed receiver and the programmable-cascaded CTLE. The core area occupies 0.26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

The paper presents a small area and low power equalizer for the high-loss serial backplane built in 65 nm CMOS technology. To mitigate the effects of channel loss and other impairments, a programmable continuous time linear equalizer (CTLE) and a programmable 5-tap decision feedback equalizer (DFE) are used in the receiver. In which DFE employs a loop-unrolling structure to meet timing constraints. Furthermore power and area savings are achieved by using two kinds of D-flip-flop (DFF) in proposed DFE and CMOS-style rail-to-rail clocking. The whole equalizer occupies 0.0091 mm2 and consumes 11-mW under a 1.2 V supply when equalizing 6.25 Gb/s data passed over a FR4 PCB channel with 10∼28 dB of loss at Nyquist frequency.

A 25Gbps single-ended to differential (S2D) low noise transimpedance amplifier (TIA) in 45RFSOI is presented. A ac-coupling capacitor and a capacitor cross-coupled pair are used to achieve S2D differential output. To optimize both noise and bandwidth, a high-gain low-bandwidth input stage followed by a continuous-time linear equalizer (CTLE) is adopted, where the CTLE uses inductive peaking and negative capacitance to achieve a bandwidth extension ratio (BWER) of 3.9 with less than 0.5dB peaking. Post simulation results show that the designed TIA achieves 63.3 dB transimpedance gain, and 22.6-GHz overall bandwidth while the photodiode capacitance is accounted for 70fF. The input average noise current spectral density is 10.9 pA/ &#x221A;Hz, and the power consumption is 38mW with 1.3V supply.