A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs

As the complexity and density of electronic components continue to increase, manual printed circuit board (PCB) routing has become an increasingly labor-intensive and costly task. However, the lack of large, publicly available datasets for training machine-learning (ML) models has hindered potential advancements in this field. To address this gap, we introduce PCBRouteNet, a comprehensive, large-scale dataset specifically designed to accelerate ML innovations in automated PCB routing. To handle the high complexity of PCB data and enhance extraction efficiency, we propose a dynamic, adjustable, quadrilateral network flow model. This model constructs a network flow graph composed of quadrilateral tiles, efficiently transforming the original design data into a network flow-based format. This format facilitates feature extraction for both global and detailed routing tasks. Additionally, we introduce and analyze various flow-encoding methods to explore the generalization and relationships between data size and network parameters, leveraging scaling laws. Our dataset features a diverse array of layouts with varying complexities, such as multilayer boards and high-density interconnects. Furthermore, we propose several practical ML tasks that utilize PCBRouteNet to demonstrate its potential in improving the efficiency and effectiveness of automated PCB routing solutions.

To improve the performance and signal integrity for printed circuit board designs, considering differential pairs in the escape routing is an important issue. Previous works use two-stage approaches, meeting points determining followed by differential pairs connecting, to generate a routing solution. However, existing approaches may produce either non-length-matching solutions or longer length-matching solutions. In this Letter, the authors propose an escape routing model with one-stage optimisation to simultaneously determine median points and route length-matching paths for all differential pairs. Experimental results show that their approach can significantly reduce maximum and average differential-pair skews with 100% length-matching results.

Given a pin-grid-array (PGA) package with an area-array of I/O pins and some devices (blocks) distributed on a printedcircuit board (PCB), the authors propose an algorithm to obtain a pin assignment solution which eases the routing in the PGA package and then improves the nets routability of PCB. In the algorithm, the routing costs of PGA package and PCB have to be calculated separately during pin assignment. A simulated annealing technique is also applied to improve the solution by exchanging the pin assignment for some chosen nets in the PGA package. Simulation results on various PCB circuits show that PCB routings produced with pin assignment under consideration can be achieved far better than the routings without pin assignment.

This paper introduces a multi-terminal escape routing algorithm for the design of Printed Circuit Boards (PCBs) that control Digital Microfluidic Biochips (DMFBs). The new algorithm is based on the principle of negotiated congestion, which has been applied in the past to problems including FPGA routing and PCB escape routing for single-terminal nets. PCBs designed for Pin-constrained DMFBs, in which one control pin may drive multiple electrodes, require multi-terminal escape routing solutions. Experimental results indicate that negotiated congestion is more effective for multi-terminal escape routing than existing techniques, which are based on maze routing coupled with rip-up and re-route, yielding an overall reduction in the number of PCB layers in most the test cases that were tried.

The conversion to lead-free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. One reliability concern becoming more prevalent is the increased propensity of pad cratering in Printed Circuit Boards (PCBs) [1, 2]. In general, lead-free solder joints are stiffer than tin-lead solder joints, and some lead-free compatible PCB dielectric materials are more brittle than conventional tin-lead compatible PCB materials. These two factors, coupled with the higher peak reflow temperatures for lead-free assembly, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath the BGA corner pads. The likelihood of pad cratering occurring in any given assembly depends on several factors including, but not limited to the BGA package size, construction and surface finish; and the PCB pad size, material and surface finish. Standard assembly level bend and shock tests can be used to determine if the entire assembly can survive a given strain and strain-rate range without having any failures. However, with these standard assembly level tests, it is difficult to determine if the failures occur due to a weaker PCB structure or a stiffer BGA package. It is critical to have a standardized test method that can be used to characterize and rank-order different PCB dielectric materials and PCB pad sizes. In this study, an easy-to-implement test method is presented in detail, along with calibration and test results comparing a broad spectrum of PCB attributes. Different dielectric materials and pad sizes were evaluated to develop a comparative metric that can be used to rank-order different material/pad size combinations. The results were generated over different pull temperatures and multiple reflows, to study the effect of temperature on dielectric mechanical strength characteristics. Ultimately, these metrics can be used to optimize PCB design, thus mitigating pad cratering potential.

Workflow of electromagnetic bandgap (EBG) common-mode (CM) filter design of edge-coupled differential pairs on a printed circuit board (PCB) and sensitivity of its characteristics to variations of geometrical and material parameters are discussed. A number of simple 20-GHz EBG CM notch filters for differential stripline pairs are designed using full-wave numerical electromagnetic modeling, fabricating, and testing. The cases of one and two stripline differential pairs crossing the EBG patches are considered. The modeled and measured mixed-mode S -parameters are analyzed as functions of geometrical parameters, including size and number of EBG patches, gaps between them, geometry and position of signal traces across the EBG patches, and thicknesses of dielectric layers. The agreement between the measured and modeled mixed-mode S- parameters validates the models and allows for further numerical experiments. It is shown that the EBG filter performance depends on various subtle technological features, e.g., conductor surface roughness on metal surfaces; length imbalance on a differential pair; rate of coupling of lines within each differential pair and between the pairs; and some other factors. The systematic analysis of the trends for filter characteristics as functions of various design parameters allows for an optimal design of the CM notch filter.

Power integrity (PI) is among the main concerns in the design process of multilayer packages and printed circuit boards (PCBs). Based on Transmission Matrix Method (TMM), the PI performance of a Ball grid array (BGA) package mounted on a PCB is investigated in this paper. The power/ground planes and the power/ground balls on a PCB and package are entirely equivalent to distributed RLGC circuits model and co-analyzed. From this model, power performance could be computed with high efficiency. Moreover, a design rule of power/ground balls arrangement is obtained by reducing the equivalent inductance and equivalent capacitance of BGA for good power integrity performance.

Accelerated temperature cycling (ATC) was used to assess the thermal fatigue reliability of a Pb free, 37.5 mm fully populated, 1295 I/O ball grid array (BGA) package assembled with backward compatible or mixed alloy (Pb free BGA/SnPb paste) processing. The Pb-free BGA components were fabricated with Sn-4.0Ag-0.5Cu (SAC 405) solder balls. The surface mount assembly was done using several custom SnPb eutectic soldering profiles designed to produce different levels of Pb mixing in the BGA solder balls. The test program also included SAC405-SAC405 assemblies for reliability comparisons. The temperature cycling and metallographic data indicate that assembly parameters that produce the lowest level of Pb mixing degrade the solder joint fatigue reliability. Failure analysis demonstrates that the lower reliability is due to poorly formed solder joints resulting from incomplete reflow. The failed solder joints exhibit inadequate BGA ball collapse, minimal Pb mixing, and fatigue failure at the printed circuit board (PCB) side of the joints instead of the package-side fatigue failures that are typical for ATC testing. The test cells with more complete Pb mixing and the pure Pb-free test cell exhibited better fatigue reliability. However, failure analysis of these samples revealed that the data were compromised by the occurrence of a second failure mode in plated through hole vias that were incorporated into the PCB test vehicle. The presence of mixed mode failures (solder joint and via) precluded direct quantitative comparisons among all the test cells. The results are discussed within the context of previously published test results from the literature, including the impact of the contribution of via failures. Recommendations are outlined for additional testing to quantify the relationships between Pb mixing level and Pb-free reliability for this high density BGA package.

Ball grid array (BGA) packages are a relatively package type and have rapidly become the package style of choice. Much high density, high I/O count semiconductor devices are now only offered in this package style. Designers are naturally concerned about the robustness of BGA packages in a vibration environment when their experience base is with products using more traditional compliant gull or J leaded surface mount packages. Because designers simply do not have the experience, tools are needed to assess the vibration fatigue life of BGA packages during early design stages and not have to wait for product qualification testing, or field returns, to determine if a problem exists. This paper emphasizes a rapid assessment methodology to determine fatigue life of BGA components. If time and money were not an issue, clearly one would use a general-purpose finite element program to determine the dynamic response of the printed circuit board (PCB) in the vibration environment. Once the response of the PCB was determined, one would determine the location and value of the critical stress in the component of interest. Knowing the critical stress, one would estimate the fatigue life from a damage model. The time required building the finite element analysis (FEA) model, conducting the analysis, and postprocess the results would take at least a few days to weeks. This is too time-consuming, except in the most critical applications. It is not a process that can be used in everyday design and what-if simulations. The rapid assessment approach proposed in this paper focuses on a physics of failure type approach to damage analysis and involves global and local modeling to determine the critical stress in the component of interest. A fatigue damage model then estimates the life. The entire fatigue life assessment is anticipated to be executed by an average engineer in real time and take only minutes to generate accurate results.

The popularity of Ball Grid Array (BGA) has been gaining momentum in the past few years. From a board assemblers' perspective, BGA offers a wide process window and low process defect rate. In the early years, the reliability of the BGA solder joints was a concern because the BGA joints are non-compliant in comparison to the joints of gull-wing QFPs. Since then many finite element analysis (FEA) and reliability studies have been published demonstrating that BGA solder joints can have adequate reliability against the shear stress caused by the mismatch of coefficient of thermal expansion (CTE). Another mode of BGA joint failure, which has not been discussed as much, is the flexure-induced failure. In a typical electronics manufacturing environment, the printed circuit boards are handled many times after surface mount and wave soldering. Hand soldering, rework, in-circuit test, functional test, and final assembly are just some of the processes before the product is eventually shipped. Most of these processes can cause bending or warping of the printed circuit assembly (PCA), On a PCA, the areas under and adjacent to the BGA components are relatively rigid compared to the rest of the board. Hence, with the same amount of board flexing, the BGA solder joints become more susceptible to fracture compared to other surface mount devices. This study employed thermal cycling, dye-penetrant test, cross-sectioning, highly accelerated life test (HALT, thermal/vibration test), highly accelerated stress auditing (HASA, thermal/vibration test), “sticky probe” with in-circuit test (ICT) fixture and strain gage measurement to investigate the failure mechanism, and to determine the effects associated with board flexure. It was discovered that excessive flexing of PCA does cause catastrophic BGA solder joint cracking. Localized board flexure during in-circuit test was found to be very high and detrimental. BGA solder joints can crack during the in-circuit test and result in opens or intermittent failures. The ICT fixture should be carefully designed and manufactured to minimize local board warp around the BGA components. A FEA tool to analyze the localized strain on the PCA can be very helpful in ICT fixture design.

Numerical simulation and fatigue life estimation of BGA packages under random vibration loading

Ball grid array (BGA) component packages challenge the circuit board design with signal routing and layout, creating in some cases extra board layers and added vias all resulting in increased costs for the printed circuit board (PCB). As component densities increase and microBGA (μBGA) and other fine pitch components become more common, microvia‐in‐pad technology will ease the transition to these fine pitch components. This paper presents and profiles a cost‐effective solution to interconnecting BGAs on PCBs using laser drilled blind vias connecting the outer three or more layers of a multilayer circuit board. Following a discussion on the design advantages, a comprehensive outline of the PCB fabrication process explores a new procedure for the rapid production of via‐in‐pad multi‐depth blind via laser drilling.

A Land Grid Array (LGA) is an area array component similar to a Ball Grid Array (BGA), but without solder balls attached to the bottom surface of the package. Due to the absence of solder balls, the LGA package has a lower thickness as compared to an equivalent BGA package. Accordingly, this reduces the thickness of the module assembly. This is a critical consideration especially for modules using stacked packages. On the other hand, the lower standoff height of the solder joints could have an impact on the performance of the package during temperature cycling. For high density modules, along with ‘minimizing’ the thickness, it is desirable to avoid increasing the package size in the length and width directions. This allows maintaining the same number of Inputs/Outputs (I/Os) as a comparable BGA device and accommodates the package on existing Printed Circuit Board (PCB) designs. For this reason, the LGA package used for the current research was identical to the BGA device that is currently used for the stacked package, but without solder balls on the bottom side. The stacked package utilizing these LGA devices and the modules were assembled using Sn3.8Ag0.7Cu lead-free solder. The reliability of the assembly was assessed using thermal cycling test. Based on the results, the first failure was recorded at the end of 1250 thermal cycles, whereas the comparable stacked package using BGA components was able to withstand 1500 cycles without failures. Dye & pry analysis was also performed on the failed stacked packages as a part of failure analysis.

Circuit design plays an essential role in all consumer electronics products. Printed circuit board (PCB) and very-largescale integration (VLSI) circuit designing requires optimization of the electronic components placement and wire routing to connect the components. Currently, circuit routing processes have been performed manually by experts, which greatly increases the cost of human resources and time. Such heuristic circuit designs are not optimized and may have errors, which is why automated circuit routing algorithms are important. However, it is difficult to obtain an optimal solution in circuit routing as it is an NPhard problem. In addition, poor circuit routing increases the wire length of the circuit, which causes an increase in circuit cost and weight as well as performance degradation. In order to achieve routing optimization, many technologies have been proposed, in which some have applied artificial intelligence (AI) to improve the overall performance and reduce the designing time. Accordingly, in this paper, routing problems in PCB and VLSI are explained, and proposed technologies to solve these routing problems are introduced. Especially, a detailed investigation and analysis of AI technologies grafted into circuit routing algorithms are explained, and the considerations for AI-based routing algorithms are presented.

Drill path optimization problem is an important problem in holes drilling with computer numerically controlled (CNC) machine. Due to the exponential increase in the number of possible solutions when the number of holes to be drilled increase, the metaheuristic optimization algorithm seems to be a good choice in solving this type of optimization problem. This paper presents a Kalman Filter approach in solving printed circuit board (PCB) routing problem by using the Simulated Kalman Filter (SKF) algorithm. The experimental results are compared with those obtained by swarm intelligence approach, which are the Particle Swarm Optimization (PSO) variants, Ant Colony System (ACS) and Cuckoo Search (CS). The implementation proves to be effortless with good global convergence capability.