A Variable Bitline Data Cache for low power design

In todaypsilas technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.

A fully power aware globally asynchronous locally synchronous network-on-chip circuit is presented in this paper. The circuit is arranged around an asynchronous network-on-chip providing a 17 Gbits/s throughput and automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each NoC units. The dynamic power consumption can be reduced up to a factor of 8 while the static power consumption is reduced by 2 decades in stand-by mode.

A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.

With the rapid evolution of network speed from 1Gbps to 10Gbps, a wide spectrum of research has been done on TCP/IP to improve its processing efficiency on general purpose processors. However, most of them did studies only from the performance perspective and ignored its power efficiency. As power has become a major concern in data centers, where servers are often interconnected with 10GbE, it becomes critical to understand power efficiency of TCP/IP packet processing over 10GbE. In this paper, we extensively examine power consumption of TCP/IP packet processing over 10GbE on Intel Nehalem platforms across a range of I/O sizes by using a power analyzer. In order to understand the power consumption, we use an external Data Acquisition System (DAQ) to obtain a breakdown of power consumption for individual hardware components such as CPU, memory and NIC etc. In addition, as integrated NIC architectures are gaining more attention in high-end servers, we also study power consumption of TCP/IP packet processing on an integrated NIC by using a Sun Niagara 2 processor with two integrated 10GbE NICs. We carefully compare the power efficiency of using an integrated NIC with using a PCI-E based discrete NIC. We make many new observations as follows: 1) Unlike 1GbE NICs, 10GbE NICs have high idle power dissipation, and TCP/IP packet processing over 10GbE consumes significant dynamic power. 2) Our power breakdown reveals that CPU is the major source of the dynamic power consumption, followed by memory. As the I/O size increases, the CPU power consumption reduces but the memory power consumption grows. Compared to CPU and memory, NIC has low dynamic power consumption. 3) Large I/O sizes are much more power efficient than small I/O sizes. 4) While integrating a 10GbE NIC slightly increases CPU power consumption, it not only reduces system idle power dissipation due to elimination of PCI-E interface in NICs, but also achieves dynamic power savings due to better processing efficiency. Our studies motivate us to design a more power efficient server architecture, which can be used in the next generation data centers.

Starting from deep submicron technologies (< 0.13μm), and even stronger in nanometer technologies, static power consumption, due to leaky “off” transistors, is becoming a non-negligible contributor to the total power dissipation. Under this condition, the total power optimization problem changes considerably. The high parallelization approach commonly used today to increase performances, will soon result in power ineffcient designs. Indeed, the static power consumption of the large number of rarely used transistors will highly penalize the total power consumption. The purpose of this thesis is to investigate the influence of static power on the design methodologies for low power. In particular, the effects of architectural as well as technology modifications are explored. The use of technology as an optimization parameter has become possible in recent technologies. In fact, they offer different threshold voltages, each one showing a different trade-off between speed and leakage current. In this work, two different frameworks are considered. In the first one, both the supply voltage and the transistor threshold voltage are freely tunable parameters. This is the most general case and corresponds to the situation where the designer has the largest freedom. In the latter framework, we assume that the designer cannot change the supply voltage nor the transistor threshold voltage and they are hence considered constants. This case corresponds to the most common one, where the designer has a supply voltage and a technology type (and hence a threshold voltage) fixed by the application and by the devices the circuit has to interface. In both cases, lot of efforts have been put to the development of a handy way to rapidly estimate the total power consumption and consequently easily compare different architectural/technology variants at the early stages of development. Examples, based on multipliers, are used extensively in the whole thesis and, at the end, the presented theory is applied to a real circuit implemented in a 90nm technology by ST Microelectronics. Measurements show a very large variability of the static power over 16 dies manufactured on the same wafer. For instance, the highest static power consumption at nominal condition (Vdd=1V, f=62.5MHz) over the lowest one corresponds to more than a factor of 2.5. Measured data also report multipliers able to work at 210mV for a frequency of 1MHz!

Due to scaling, many limitation arise for CMOS-based design memory cells in the nanometre regime, i.e. it becomes necessary to find a substitute for this design. Low power and high speed integrated circuits (ICs) are the demand of the electronics industry in many applications such as Internet of things (IoT) and electronics gadgets, e.g. Mobile, Laptops etc. Now, modern design ICs uses carbon nanotube FET or FinFET to design memory cells because of their excellent features of having low leakage and delay and improved performance. In this paper, two 10 transistor (10 T) FinFET design SRAM cells are proposed along with their hold, read, and write static noise margins (HSNM, RSNM, and WSNM), dynamic and static power consumption. These cells consume low power and provide high stability for electronic gadgets. In the proposed cells, we used a separate read and write path and back gate control method (BG). A comparative analysis of the proposed cells is done with the existing 10 T CMOS and FinFET based cells. All cells are simulated by using the tool HSPICE at 32 nm technology for a supply of 0.5 V. Cells 1 and 2 dissipate 69% and 85% less static power, 54% and 68% less read power and 17% and 56% less write power, respectively, compared to the 10 T FinFET cell. Results signify that the proposed independent gate (IG) FinFET based cells have the highest value of margins and the least value power consumption.

Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique to reduce both static and dynamic power consumption in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current during the scan shift process, and this vector can also be used to reduce dynamic power. However, the reverse is not always true. A heuristic algorithm is presented to find such vectors. The proposed method is simulated by SPICE with BPTM 22nm transistor model, and the results show that on the average 15% total power reduction is achievable by the proposed method.

In autonomous robots, the hardware and the algorithms are limited by the power constraints of the robots. Increasing algorithm efficiency can be considered as a way to deal with power constraints. Considering the processing load of Visual SLAM methods, which are frequently used in autonomous robots and become increasingly widespread, there is a need to investigate the effects of methods on power consumption. In this study, a performance comparison of ORB-SLAM2, which is a feature-based Visual SLAM method, DSO, and LDSO, which are direct Visual SLAM methods was conducted. We perform the comparison on ICL-NUIM, KITTI, and EUROC datasets using NVIDIA Jetson TX1 hardware. Central Processor Unit (CPU) usage, Graphics Processor Unit (GPU) power consumption, and total power consumption were taken into account since hardware and power constraints are very important issue for autonomous systems. Results showed that ORB-SLAM2 is the most efficient method for GPU load and power consumption. GPU power consumption and total power consumption are higher than expected for the DSO method compared to CPU load. The computational cost of Loop-Closure is seen clearly when comparing the DSO and LDSO methods.

Achieving energy efficiency is of paramount importance in facilitating the deployment of artificial intelligence (AI) applications, particularly for edge devices. The computational complexity and memory requirement of AI workloads have made energy efficiency in circuits the primary design constraint, prompting a need for architectural reconsideration. However, operations in Convolutional Neural Networks (CNN) relying on matrix multiplication offer opportunities for algorithm-level optimization. The dynamic power consumption in CMOS technology exhibits a direct correlation with the switching activities (SA) associated with transitions of data bits from one cycle to the next. Minimizing SA constitutes an effective approach to curbing power consumption, resulting in prolonged battery life. This work introduces a cross-layer end-to-end optimization technique, which involves a one-time sorting of pre-trained model parameters to reduce switching activity during matrix multiplication or convolution operations while eliminating the indexing overhead during inference. While upto 40% reduction in switching activities through sorting has been achieved, the actual saving in dynamic power achievable for the input stationary systolic array is approximately 10% in total power consumption and around 15% in switching power. The proposed method has been validated using various pre-trained networks, including GoogeLeNet, MobileNet, AlexNet, and SqueezeNet, among others.

This paper presents a QRS detector operating in multi-mode with low complexity, power saving consumption for implantable pacemaker IC. The complexity of detector is optimized after testing dynamic range of internal signals. Correspondingly, static power consumption is reduced significantly. The dynamic power consumption is saved by using down-sampling rate structure and turning off de- active filter banks bases on noise estimation. This QRS detector is evaluated with MIT-BIH Arrhythmia database archives >99% detection ratio. A soft IP core is prototyped on FPGA and synthesized by Samsung 0.18um standard library.

A new scheme to reduce the power consumption of static random access memories is presented. It is shown that using segmented virtual grounding (SVGND), it is possible to reduce both dynamic and static power consumption. The leakage power of the cells is reduced by reducing the voltage drop over a cell. The dynamic power dissipation is also reduced by eliminating the power consumption due to the discharge of the nondesired neighboring bitlines. The effectiveness of this scheme is compared to recently reported low-power schemes. It is shown that unlike those schemes, SVGND can accommodate multiple words in one row; a significant improvement in soft error rate tolerance

Personal portable devices such as DMB (digital multimedia broadcasting)s, PMP (portable multimedia player)s and PDA (portable digital assistant)s require long battery life without reducing their performance. Power consumption is one of important factors in ubiquitous environments. To reduce the dynamic power consumption, many researches have been conducted on the dynamic voltage and frequency scaling (DVFS). DVFS can reduce the power consumption proportionally to the square of the supply voltage. But processor operation under the critical speed increases the leakage current. Larger leakage current increases the static power consumption. This paper proposes a new power-aware scheduling algorithm that reduces the static and dynamic power consumption to use frequency scaling between two discrete voltage levels and under the critical speed while meeting the deadline of given applications. The simulation and experimental implementation show that the proposed scheduling algorithm results in up to 25% energy gains over traditional DVFS algorithms with two task scheduling policies.

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to reduce the power consumption. By using this method, we manage to save power by up to 45.7% compared to a baseline architecture without any performance loss.

Current superscalar processors access the BTB early to anticipate the branch/jump target address. This access is frequent and aggressively performed since the BTB is accessed every cycle for all instructions in the ICache line being fetched. This fact increases the power density, which could create hot spots, thus increasing packaging and cooling costs. Power consumption in the BTB comes mostly from its two main fields: the tag and the target address fields. Reducing the length of either of these fields reduces power consumption, silicon area and access time. This paper analyzes at what extent tag and target address lengths could be reduced to benefit both dynamic and static power consumption, silicon area, and access time, while sustaining performance. Experimental results show that the tag length and the target address could be reduced by about a half and one byte, respectively with no performance losses. BTB peak power savings can reach about 35% when both reductions are combined together, thus effectively attacking the hot-spot.

Power consumption during test mode is much higher than in normal mode of operation. This paper addresses issue of assigning suitable values to the unspecified bits (don't care) in the test patterns so that both static and dynamic power consumption during testing is reduced. We have used a genetic algorithm based heuristic to fill the don't cares. Our approach produces an average percentage improvement of 31.9, 37.0, and 37.7 in dynamic power and 3.0, 7.4, and 5.3 leakage power over 0-fill, 1-fill, and MT-fill algorithms for don't care filling, considering the test patterns having unspecified bits in ISCAS'89 benchmark suite.