A Wide-band Reference-less Bidirectional Continuous-Rate Frequency Detector

The complexity and variability of streaming data have brought a great challenge to the elasticity of the data processing systems. Streaming systems, such as Flink and Storm, need to adapt to the changes of workload with auto-scaling to meet the QoS requirements while saving resources. However, the accuracy of classical models (such as a queueing model) for QoS prediction decreases with the increase of the complexity and variability of streaming data and the resource interference. On the other hand, the indirect metrics used to optimize QoS may not accurately guide resource adjustment. Those problems can easily lead to waste of resources or QoS violation in practice. To solve the above problems, we propose AuTraScale, an automated and transfer learning auto-scaling solution, to determine the appropriate parallelism and resource allocation that meet the latency and throughput targets. AuTraScale uses Bayesian optimization to adapt to the complex relationship between resources and QoS, minimizing the impact of resource interference on the prediction accuracy, and a new metric that measures the performance of operators for accurate optimization. Even when the input data rate changes, it can quickly adjust the parallelism of each operator in response, with a transfer learning algorithm. We have implemented and evaluated AuTraScale on a Flink platform. The experimental results show that, compared with the state-of-the-art method like DRS and DS2, AuTraScale can reduce 66.6% and 36.7% resource consumption respectively in the scale-down and scale-up scenarios while ensuring QoS requirements, and save 13.5% resource on average when the input data rate changes.

Sub-sampling PLLs (SSPLLs) are popular for generating low-jitter output signals. However, the critical problem of SSPLLs is that they do not use a frequency divider, so the lock-in range is strictly limited. The lock-in range is defined as the maximum instantaneous disturbance at which the PLL can recover its output frequency, f OUT , to the target frequency, f TA , [1], and the lock-in range of SSPLLs generally is restricted to less than 40% of the reference frequency, f REF [2]. As shown at the top left of Fig. 17.8.1, if a sudden frequency disturbance, f D , occurring through the supply or the control voltage is within the lock-in range, it can be corrected by the PLL, allowing f OUT to be recovered as f TA . However, if f D exceeds the lock-in range, it causes lock failure or false locking. As f OUT increases, the external disturbance with the same magnitude causes a larger f D which implies that the problem of the lock-in range is more serious when we aim for a higher f OUT given f TA . Despite their popularity, conventional frequency-locked loops (FLLs) [3], [4] require large power due to dividers operating at f OUT , To save power, the FLL in [2] operates once every 200 reference cycles, but this method has a problem in that the f D -detecting time increases in inverse proportion to the duty cycle of the FLL, which increases the overall frequency re-acquisition time, f RA . Another solution is to extend the lock-in range by increasing f REF However, when a reference multiplier is used in a conventional way, it requires large power, since every edge at the output must have very low jitter [5] to avoid deteriorating the PLL output jitter. It also degrades the resolution of the f OUT of integer-N PLLs [6].

Thispaper presents a 200-Mb/s to 3-Gb/s half-rate referenceless clock and data recovery (CDR) circuit in 180nm CMOS process. A bidirectional frequency detector (FD) is proposed to eliminate the harmonic locking issue and reduce the frequency acquisition time. A frequency band selectorfor wide-range the voltage-control oscillator (VCO) is also presented to select an exact frequency band of the VCO. The simulation shows the CDR achieves 10-ps peak-to-peak jitter at 3Gb/s and the frequency acquisition time of 12.9 μs.

The CDR circuit is a key enabling block in high-speed serial links. With an external reference clock for frequency acquisition, high-performance CDR circuits typically operate at a single pre-defined data rate. In rapidly growing telecommunication applications, however, it is desirable for a CDR circuit to be able to cover a wide range of bit rates for improved flexibility. In the WDM technique, for example, the data can be transmitted with different bit rates. Thus, it is desired that the CDR circuit detects the change in the input data rate and automatically acquire the new data rate without any need for external programming.

This paper presents a time-domain closed-loop resistive temperature sensor architecture. The design employs a frequency-locked loop (FLL)-based oscillator as the sensing element, generating a monotonic frequency response to temperature variations. The output frequency is digitized on-chip and converted into a temperature code. Within the oscillator core, a switched-capacitor technique converts frequency to voltage for closed-loop control, reducing charging/discharging voltage swings and significantly lowering dynamic power consumption. The FLL topology enhances frequency stability, minimizes distortion, and suppresses power supply sensitivity. Fabricated in a 180 nm CMOS process with a core area of 0.12 mm2, the sensor achieves a peak-to-peak inaccuracy of +1.2 °C/−0.9 °C from −40 °C to 125 °C. Operating at 1 V, the circuit consumes only 10 μW with a resolution of 51 mK within 12 ms.

This brief describes a compact and precise resistive temperature sensor based on a frequency-locked loop (FLL) intended for thermal monitoring in system-on-chips. The FLL incorporates a switched-capacitor loop filter improving the sensor’s inaccuracy and FLL outputs are converted into a digital code with an edge-combined counter for efficient frequency-to-digital conversion. A prototype sensor is fabricated in 65-nm CMOS process and occupies only 6, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$400 \mu \text{m} ^{\mathrm{ 2}}$ </tex-math></inline-formula> . It achieves a one-point trimmed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\sigma $ </tex-math></inline-formula> inaccuracy of ±0.64 °C over a wide temperature range of −50 to 125 °C. Operating at 0.9 V supply, it consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40 \mu \text{W}$ </tex-math></inline-formula> and achieves 2.2 mK resolution in a 1-ms conversion time, which corresponds to a resolution FoM of 0.19 pJ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot \text{K} ^{\mathrm{ 2}}$ </tex-math></inline-formula> .

This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With input 10-Gb/s data of a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 μs. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage.

Internet based applications are mostly based on a reliable transport service. TCP (transmission control protocol) is one of the protocols responsible for applications performance. Mobile users access to Internet services through 2.5 and 3 Generation networks, which have a significant latency due to error mechanisms introduced at the link layer, as well as transmission delays in the radio access networks. High latency produces interaction with timers of upper protocols. Data rate is other limiting characteristic on these networks. Moreover, data rate changes during a TCP connection due to mobility. TCP can adapt its rate when slow data rate changes thanks to its self-clocking propriety. In case of a sudden change, TCP performance is degraded due to spurious retransmission, and the activation of its congestion control mechanisms. This paper will show the effects and optimization of some TCP parameters over GPRS (general packet radio service) and 802.11b real networks.

Design and analysis of low-phase-noise low quadrature error V-band subharmonically injection-locked quadrature voltage-controlled oscillator (QVCO) and quadrature frequency-locked loop (FLL) are presented in this paper using 90-nm CMOS process. A modified self-injection technique is employed in the QVCO to reduce quadrature error and phase noise. A transformer coupled topology is adopted to widen the locking range (LR) of the subharmonically injection-locked QVCO. With a subharmonic number of 3, the proposed subharmonically injection-locked QVCO demonstrates an overall LR of 3.5 GHz, a phase noise of −126.8 dBc/Hz at 1-MHz offset, a phase error of 0.32°, and an amplitude error of 0.26 dB. Moreover, the quadrature FLL is developed using the QVCO, and the subharmonic number can be up to 32 since the control voltage of the QVCO is adaptively aligned to overcome the LR. The operation frequency of the subharmonically injection-locked quadrature FLL is from 49 to 51.4 GHz. The measured amplitude and phase errors are 0.5 dB and 2.5°, respectively. Between 15 °C and 50 °C, the measured minimum phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are lower than −106 dBc/Hz and 110 fs, respectively. Compared to the prior art, the proposed $V$ -band subharmonically injection-locked quadrature QVCO and quadrature FLL feature excellent performance and good robustness.

The paper presents frequency stabilization of a VCDRO operating at 11 GHz by using a frequency lock loop supported by microcontroller. The signal from a PLL synthesizer is used as a reference signal in the FLL in order to obtain a signal with characteristics like one originating from a free- running VCDRO having, in the same time, stability close to a signal from PLL. The two signals are compared at 40 MHz band where a IF filter is designed in order to limit a stability difference between a VCDRO and PLL. A control signal within the FLL loop is realized with microcontroller that ensures a very stable operation over a wide temperature range. The signal obtained in the presented way meets the desired stability with very low level of spurious signals and meets all requirements for LO signals in modern microwave systems.

This paper deals with a single phase grid interfaced SPV (Solar Photo Voltaic) system. The proposed multifunctional system also helps in power quality improvement in single phase distribution system. A two stage system is used in the presented work. The first stage is a boost converter, which serves the purpose of MPPT (Maximum Power Point Tracking). The second stage is a VSC (Voltage Source Converter), which performs reactive power compensation, harmonics elimination and feeding solar energy into the grid. A SOGI-FLL (Second Order Generalized Integrator with Frequency Lock Loop) based control algorithm is proposed for control of VSC. A feed forward term for solar contribution is used to improve the dynamic response. A PI controller is used to regulate the DC link voltage to desired value. A wide range of simulation studies are carried out to show all features of proposed system. The system is tested considering realistic non-ideal grid conditions. The performance of proposed system is found satisfactory for wide variation in grid voltage. The THD of grid current is well under IEEE-519 standard.

Nowadays, vehicles are not only merely used as a transportation medium, but also as a highly mobile Internet of Things (IoT) node, collecting data from all types of sources. The delivery of aggregated vehicle sensor data into the cloud for further analysis is very fragile, as vehicles move fast in their environment and channel conditions vary heavily. Next to mastering possible packet loss, communication protocols need to quickly adapt to the frequent data rate changes. Random Linear Network Coding (RLNC) has been proven as an efficient and robust mechanism for reliable data transfer especially on lossy channels. In this paper, the authors extend the Scalable Network Coding (ScalaNC) framework with the novel congestion control Bottleneck, Bandwidth and Round-Trip Time (BBR) in order to quickly adapt to the frequent changes in data rate and allow effective transfer of high amounts of data from vehicles and into the cloud. ScalaNC is validated in a Hardware-in-the-Loop field test consisting of a Long Term Evolution (LTE) base station and channel emulator.

A self-clocked unified voltage-and-frequency regulator (UVFR) is proposed to provide a highly correlated voltage-and-clock pair and to guarantee error-free operation of an arbitrary in-order executed digital load. Built on a digital low-dropout regulator (D-LDR), the unified control loop is highly synthesizable and adaptively clocked to achieve both fast transient response and low quiescent current. Replica frequency-locked loops (FLLs) and hysteresis switching logic (HSL) are employed to compensate for the built-in offset of conventional beat-frequency (BF) quantization and provide calibration-free regulation to tolerate global and random variations. Fabricated in a 65-nm CMOS process, the proposed UVFR reduced the voltage undershoot by 25%, reduced the steady-state offset by 84%, and achieved a 5.9X wider adaptive clocking range compared to the baseline with the help of our proposed replica FLLs and HSL.

This chapter introduces the concept of on-chip frequency generation based on the thermal properties of silicon. Thermal-diffusivity of silicon, D, will be introduced as the rate at which heat diffuses through a silicon substrate. It will be described how an electrothermal filter (ETF) harnesses this physical property in order to produce accurate on-chip delays. The design of a practical ETF within standard CMOS processes will be described. It will be shown that an ETF behaves like a low-pass filter with a defined phase shift, which is a combined function of its geometry and D. Furthermore, a method of frequency generation based on an electrothermal frequency-locked loop (FLL) will be introduced. Such loop locks the output frequency of a variable oscillator to the phase shift of an ETF.

This paper describes the operation of an algorithm for synchronizing the time of computers using messages transmitted over packet-switched networks such as the Internet. The algorithm configures itself to realize any specified performance level at minimum cost (measured in computer cycles or network bandwidth). If the highest possible accuracy is requested, the performance will be limited by the larger of the instability of the local clock oscillator or the noise in the measurement process between the client and the server; uncertainties of about 8 ms RMS have been obtained using standard workstations and average network connections. Lower accuracy can be realized at substantially lower cost because the cost varies approximately as the inverse of the accuracy squared over a wide range of these parameters. The algorithm makes better use of scarce network bandwidth than previous methods. This improvement is realized by using a pure frequency-locked loop (rather than mixed frequency/phase locking algorithms currently proposed for the NTP) with unequal spacing between calibration cycles. The result is a cleaner separation between network noise and clock noise, which is especially important when the highest possible accuracy is desired. In addition, the algorithm is an improvement over the pure-FLL "Interlock" algorithm described previously because it is self configuring. In addition to supporting an explicit trade-off between cost and accuracy, the algorithm provides better performance than previous methods because it is better able to adapt itself to fluctuations in the asymmetry of the network delay.