Accurate diode behavioral model with reverse recovery

Compact Modeling of Physical Mechanisms Present in the Weak Breakdown Regime of Advanced Si and SiGe Bipolar Transistors

Compact models of semiconductor devices play a crucial role in design and analysis of large circuits. This paper presents a qualitative study of diode compact models including temperature dependency and reverse recovery phenomenon. The comprehensive behaviour of p-n junction diode is captured using Verilog-A language which is compatible to standard SPICE simulators. In this work, three types of diode models have been investigated based on temperature scale. Similar to SPICE compact models, a set of tuneable parameters are defined and presented for each type. In addition, an extensive study of reverse recovery has been done to determine the magnitude of reverse current and to evaluate model parameters like charge storage time and transition time based on input switching and temperature. Simulation results show that the developed model in this work is compatible like standard compact model scalable with area, temperature and intrinsic carrier concentration.

This paper presents the reverse recovery characteristic according to the change of switching states when Si diode and SiC diode are used as clamp diode and proposes a method to minimize the switching loss containing the reverse recovery loss in the neutral-point-clamped inverter at low modulation index. The previous papers introduce many multiple circuits replacing Si diode with SiC diode to reduce the switching loss. In the neutral-point-clamped inverter, the switching loss can be also reduced by replacing device in the clamp diode. However, the switching loss in IGBT is large and the reduced switching loss cannot be still neglected. It is expected that the reverse recovery effect can be infrequent and the switching loss can be considerably reduced by the proposed method. Therefore, it is also possible to operate the inverter at the higher frequency with the better system efficiency and reduce the volume, weight and cost of filters and heatsink. The effectiveness of the proposed method is verified by numerical analysis and experiment results.

The way from the compact model development to implementation into a commercial circuit simulator is often time consuming. Moreover, it is not always straightforward how to implement behavior models in SPICE-like simulators. A capability of the analog hardware description language (AHDL) Verilog-A to handle state-of-the-art compact bipolar transistor modeling mixed with behavioral substrate coupling modeling has been demonstrated.

An improved lumped-charge model of PIN diodes is described. This model includes reverse and forward recovery, emitter recombination and boundary-moving effects. Especially for reverse recovery, both sweeping out and recombination effects are taken into account Based on the model, most parameters can be extracted by a new accurate curve-fitting approach, and the other can be obtained by simple experiments. Comparison between simulation and experimental results for transient behavior verifies the model and the parameter extraction approach.

A compact spice model of the phase change memory with the crystalline fraction as the switching by Verilog-A language is proposed and demonstrated. The model can simulate not only the resistance change by the different electrical pulse, but also the temperature profile and crystalline fraction during programming operation. The simulated resistance as a function of the amplitude of programming voltage pulses is in good agreement with the experimental data.

Variability and degradation in RRAM devices involve complex physical mechanisms that depend on the device, environment and programming/read operation. The development of solid and accurate compact models, ready to be used in standard circuit simulators, requires the meticulous emulation of this kind of non-ideal effects. In this work we present an advanced approach for the emulation of complex variability and degradation effects in SPICE compacts models. Without requiring compiled components — such as Verilog-A or CMI code — the proposed solution can be adapted to any kind of memristor model providing full support to the emulation of these intricate behaviors. Thorough experiments illustrate the capabilities of the presented approach. There, we make use of a physical SPICE model that emulates behavioral dependence on the device cycling, simulation time and stress levels. After applying the proposed techniques, we obtain an enhanced model properly aware of the device's non-ideal behavior.

This paper presents a large-signal hetrojunction bipolar transistor model for III-V technologies. A standard HBT compact model is demonstrated accurate in most regions of operation. At low collector supplies and high input drive levels, however, the compact model fails to accurately predict largesignal RF performance. Model inaccuracies are, through largesignal network analyzer measurements, attributed to minority carrier injection due to forward biased base-collector junction; a phenomenon which is not accounted for in the compact model. A hybrid model is proposed. This is a combination of the standard compact model and an artificial neural network based behavioral model. The artificial neural network is trained to empirically model minority carrier injection in the base-collector junction. Significant accuracy improvement is demonstrated and it is verified that greater accuracy comes at the expense of a very small degradation in execution speed.

An up-to-date summary of relevant large signal (LS) or nonlinear models for power amplifier design is provided, covering a wide range of device types, along with a brief history for the various categories of models. Addressed are compact LS models for III–V as well as silicon FETs and bipolar transistors that are suitable for power amplifier design, utilizing a range of technologies including GaN, GaAs, SiGe and CMOS. Behavioral LS models are considered along with trade-offs that often exist as compared to compact models. Important developments of related technologies that have had significant impact on large signal modeling such as automated small and large signal network analyzers, wafer probe capability, and harmonic balance simulator software are also discussed.

The temperature range of SPICE models of bipolar and field-effect transistors is extended from the standard commercial level ( -60 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C⋯+150 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C) to harsh conditions level ( -200 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C⋯+300 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C) for low/high-temperature ICs design. This is done by including additional equations for temperature-dependent parameters, and by connecting additional elements to the device equivalent circuit to take into account the thermal effects. The universal automated methodology of model parameters extraction from the experimental data measured at low and high temperatures is proposed. The good agreement between simulated and measured device characteristics is achieved. The RMS error is not more than 10%-20%.

As power electronic engineers increase the switching speed of voltage source converters for the purpose of higher power density, the dI/dt and dV/dt across the power semiconductors increases as well. A well-known adverse consequence of high dV/dt is parasitic turn-on of the power device in the same phase leg as the device being triggered. This causes a short circuit with high shoot-through current, high instantaneous power dissipation and possibly device degradation and destruction. It is critical for converter designers to be able to accurately predict this phenomenon through diagnostic and predictive modelling. In this paper, a physics-based device and circuit model is presented together with experimental results on parasitic turn-on of IGBTs in voltage source converters. Because the model is physics based, it produces more accurate results compared with compact circuit models like SPICE and other circuit models that use lumped parameters. The discharge of the Miller capacitance is simulated as a voltage dependent depletion capacitance and an oxide capacitance as opposed to a lumped capacitor. The model presented accurately simulates IGBT tail currents, PiN diode reverse recovery and the non-linear miller capacitance all of which cannot be solved by lumped parameter compact models. This is due to the fact that the IGBT current in the model is calculated using the Fourier series based re-construction of the ambipolar diffusion equation and the miller capacitances are calculated using fundamental device physics equations. This paper presents a physics-based device and circuit model for parasitic turn-on in silicon IGBTs by numerically modelling the minority carrier distribution profile in the drift region. The model is able to accurately replicate the transient waveforms by avoiding the use of lumped parameters normally used in compact models.

This paper mainly studies T/R (Transmitter and Receiver) module in radar and its internal solid-state microwave power device, and the mechanisms of performance parameters' change affected by temperature. First, we establish a compact model of solid state microwave power FET (Field Effect Transistor). Second, based on the compact model, a behavioral model of T/R module is developed. By simulating the behavioral model, trends of performance parameters of T/R module under varied temperature conditions can be analyzed. Last, we conduct a series of experiments to verify the behavioral model. Above all, our study aims to provide a reference for the design, analysis and operational reliability of T/R module.

A deep learning-based parameter extraction for industry standard BSIM-CMG compact model is presented in this paper. A Monte-Carlo simulation varying key BSIM-CMG parameters was performed to create the 1 million I-V sweep data for training. A deep Learning model is trained with drain current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> as an input and the BSIM-CMG parameters as the output. The trained neural network was able to successfully model TCAD I-V data. The results show very promising capability of the deep learning-based parameter extraction to develop compact models within seconds with less or comparable error compared to traditional manual parameter extraction.

Analog and RF design building blocks for space applications require very accurate prediction of SiGe HBT device behavior in this extreme environment. The ability of two industry standard bipolar compact models to represent the SiGe HBT in an extreme temperature environment was evaluated. It was determined that neither the Mextram or VBIC industry standard models were able to accurately represent the SiGe HBT's device performance over the extreme cold temperature environment. For initial design work a model binning approach was taken, where multiple models were required to represent the SiGe HBT over the full cryogenic temperature range. Each of the industry compact models was fitted over a limited temperature range. As the temperature range decreased the accuracy of the model decreased.

The artificial neural network (ANN)-based compact model has significant advantages over physics-based standard compact models such as BSIM-CMG because it can achieve higher accuracy over a wide range of geometric parameters. This makes it particularly suitable for design space exploration and optimization. However, the ANN-based compact model using only one set of model parameters (global-ANN) requires larger model sizes to achieve wider coverage and higher accuracy in order to capture the unpredictable nonlinearities of emerging devices. This results in reduced simulation speed and a trade-off between simulation accuracy, model coverage, and simulation speed makes it difficult to utilize ANN-based compact models in a variety of ways. To solve this problem, we propose the first ANN-based compact modeling flow using a binning method (binning-ANN) and we address the training requirements and data sparsity issues that may occur due to the binning method in ANNs. In addition, we develop a bin size optimization guideline for the binning-ANN. As a result, the binning-ANN not only has higher accuracy, but also much better expandability than existing methods.