Across field CD control improvement for critical level imaging: new applications for layout correction and optimization

Scatterometry has been most commonly applied to CD metrology of line/space grating structures. However, for the process development and control of 3D structures for contact hole lithography applications, the current metrology methods of CD-SEM, electrical CD (ECD) and/or cross-sectional SEM (X-SEM) produce the desired information either (a) as an incomplete solution, (b) too late in process flow, or (c) in a destructive manner. In this paper, we will present use cases for the application of scatterometry to 3D structures, i.e., post-lithography hole/space patterns, where measurements of CD, profile, and film thickness can be made immediately following the lithography process, in a method nondestructive to the wafer. These use cases demonstrate the capability of 3D metrology integrated onto a TEL Clean Track platform, where a Therma-Wave reflectometer was used to generate spectra that were then processed via Timbre ODP, for a film stack of patterned photoresist (PR), anti-reflective coating (ARC), and oxide on top of a silicon (Si) substrate. Focus-Exposure Matrix (FEM) wafers have also been produced in order to characterize the contact hole profile and CD variation as a result of changing focus and exposure conditions. The results of the experiment show that ODP can be used successfully to monitor CD, film thickness, and profile variation, providing a valuable solution to contact hole lithography. Tool precision and matching results are also shown, which indicate the stability of the measurement process, and correlation to CD-SEM is also provided as a reference metrology. These results suggest that integrated 3D scatterometry is a viable production metrology solution, enabling the progression toward Advanced Process Control (APC).

Manufacturing-time process (P) variations and runtime voltage (V) and temperature (T) variations can affect a DRAM's performance severely. To counter these effects, DRAM vendors provide substantial design-time PVT timing margins to guarantee correct DRAM functionality under worst-case operating conditions. Unfortunately, with technology scaling these timing margins have become large and very pessimistic for a majority of the manufactured DRAMs. While run-time variations are specific to operating conditions and as a result, their margins difficult to optimize, process variations are manufacturing-time effects and excessive process-margins can be reduced at run-time, on a per-device basis, if properly identified. In this paper, we propose a generic post-manufacturing performance characterization methodology for DRAMs that identifies this excess in process-margins for any given DRAM device at runtime, while retaining the requisite margins for voltage (noise) and temperature variations. By doing so, the methodology ascertains the actual impact of process-variations on the particular DRAM device and optimizes its access latencies (timings), thereby improving its overall performance. We evaluate this methodology on 48 DDR3 devices (from 12 DIMMs) and verify the derived timings under worst-case operating conditions, showing up to 33.3% and 25.9% reduction in DRAM read and write latencies, respectively.

Lithographic patterning of small inlaid trenches is becoming increasingly important for leading edge semiconductor manufacturing. Correct patterning of these small inlaid features is made difficult by inherent difficulties in darkfield pattern imaging, large substrate reflectivity variations, large sensitivity to reticle CD variations and stringent requirements for the photoresist etch mask. Additionally, successful process optimization requires accurate knowledge of the lithographic errors affecting CD control. We present her a CD control error budget analysis for 0.18 um inlaid trench lithography using 0.6 NA 248 nm exposure tools and high resolution chemically amplified resist. Experiment and tuned simulation are used to translate tool, process and reticle variations into wafer CD variations. Results of across-field and across-wafer error analysis for different process choices are presented as are experimental verifications of their accuracy. Conclusions presented include the significant impact of stepper best- focus determination for across-field CD variation and the considerable overall CD control improvements observed with thin photoresist and strong phase shift processes.

The insertion point for the first scattering bar is a key point in the development of a process using assist features, because this semi dense feature will determine the overall depth of focus of the process. A study of the parameters, which influence the choice of this insertion point, has been performed using a 0.63 NA 193 nm scanner for a 100 nm CD target after litho. The impact of the scattering bar on: Depth of Focus, Energy Latitude, Mask Error Enhancement Factor, printability, and the effect of scattering bar line width variation on main feature described by a parameter called AFMEEF will be discussed in this paper. The optimal insertion point for the first scattering bar will strongly depend on the litho-graphic process and the mask parameters. A model is proposed to determine the optimal insertion point, as function of the dose, focus budget, minimal allowed scatterbar width, and mask CD dispersion for both scattering bars and main features.

At the early stage of a new technology development, Ground Rule (GR) calculations are performed assuming design targets are met, and all the process variations are within certain process assumptions. However, as technology matures, it is expensive, and time consuming to verify these assumptions for all the designs allowed by the rules. Thus, there’s a loop hole in the GRs if these assumptions are not met on the design. This issue becomes even worse for 2D dense design such as SRAM, where the design target and wafer image are so different due to all the corners, jogs, line ends etc, and the process variations are much larger for the 2D designs. As a result, SRAM designs almost never follow a standard GR approach but its own unique rules. In fact, for SRAM designs of slightly different style, the rules will be significantly different. On the other hand, Process Variation (PV) contours offer much more details of process variations even though their usage is very limited. One reason for that is that off-nominal conditions having larger risks from rule point of view but have lower probability at the same time, making it a dilemma for us. In this talk we propose a method to incorporate PV contours in GR calculation, and each PV contour are used in Monte-Carlo calculation in accordance with its own probability. We apply this method in SRAM layout optimization as an example. This work was performed at the IBM Semiconductor Research Center, Albany NY 12203

As VLSI technology scales towards 65 nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people often treat systematic components of the variations, which are generally traceable according to process models, in the same way as random variations in process corner-based methodologies. In particular, lithography-induced process variations are usually estimated by a universal worst-case value without considering their layout environment. Consequently, the process corner models based on such estimation are unnecessarily pessimistic. A new ASIC design methodology that captures lithography-induced polysilicon gate length variations including both the layout dependent systematic components and random components is proposed. This methodology also shows that lookup table methodology is sufficient to handle back end of line lithography process variations in timing analysis. In addition, a new technique of dummy poly insertion is suggested to shield inter-cell optical interferences. This technique together with standard cells characterised using the new methodology will let current design flows comprehend the variations almost without any changes. More importantly, by separating systematic lithography effect from random process variations, this methodology greatly reduces pessimism in timing analysis, thus enabling both aggressive design implementation and easier timing signoff. Experimental results on industrial designs indicate that the new methodology can averagely reduce timing variation window by 11% and power variation window by 55% when compared with a worst-case approach.

Overlay errors, cut/block and line/space critical-dimension (CD) variations are the major sources of the edge-placement errors (EPE) in the cut/block patterning processes of complementary lithography when IC technology is scaled down to sub-10nm half pitch (HP). In this paper, we propose and discuss a modular technology to reduce the EPE effect by combining selective etching and alternating-material (dual-material) self-aligned multiple patterning (altSAMP) processes. Preliminary results of altSAMP process development and material screening experiment are reported and possible material candidates are suggested. A geometrical cut-process yield model considering the joint effect of overlay errors, cut-hole and line CD variations is developed to analyze its patterning performance. In addition to the contributions from the above three process variations, the impacts of key control parameters (such as cut-hole overhang and etching selectivity) on the patterning yield are examined. It is shown that the optimized altSAMP patterning process significantly improves the patterning yield compared with conventional SAMP processes, especially when the half pitch of device patterns is driven down to 7 nm and below.

The move to low-k1 lithography makes it increasingly difficult to print feature sizes which are a small fraction of the wavelength of light. Manufacturing processes currently treat a target layout as a fixed requirement for lithography. However, in reality layout features may vary within certain bounds without violating design constraints. The knowledge of such tolerances, coupled with models for process variability, can help improve the manufacturability of layout features while still meeting design requirements. In this paper, we propose a methodology to convert electrical slack in a design to shape slack or tolerances on individual layout shapes using a two-phase approach. In the first step, we redistribute delay slack to generate delay bounds on individual cells using linear programming. In the second phase, which is solved as a quadratic program, we convert these delay bounds to shape tolerances to maximize the process window of each shape. The shape tolerances produced by our methodology can be used within a process-window optical proximity correction (PWOPC) flow to reduce delay errors arising from variations in the lithographic process. Our experiments on 45nm SOI cells using accurate process models show that the use of our shape slack generation in conjunction with PWOPC reduces delay errors from 3.6% to 1.4%, on average, compared to the simplistic way of tolerance band generation.

A review of the method, results, and possible benefits of the directed assembly of block copolymers on lithographically defined, chemically nanopatterned substrates. Insertion of block copolymers into the lithographic process showed the potential to reduce critical dimension variation in the lithographic process by correcting for process variations in the original lithographically defined pattern. The ability of directed assembly of block copolymers to yield a variety of device oriented patterns while maintaining registration to the substrate and a high degree of perfection was demonstrated. Directed assembly of block copolymers was also able to generate structures that do not naturally occur in the bulk, such as square arrays of cylindrical domains and quadratically perforated lamellae.

Failure due to aging mechanisms is an important concern for RF circuits. In-field aging results in continuous degradation of circuit performances before they cause catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is determined not only by aging at the device level but also by the slack in the specifications, process variations, and the stress conditions on each of the devices. In this paper, we present a methodology for analyzing, monitoring, and recovering performance degradation in cross-coupled $\text{LC}$ oscillators caused by aging mechanisms in MOSFET devices. At design time, we identify reliability hot spots and concentrate our efforts on improving these components. We also identify the circuit variable that is easy to measure but highly correlated to the performance of the primary circuit and codesign the monitoring and reconfiguration mechanism along with the primary circuit. Experimental results with a fabricated oscillator chip show that the phase noise of the oscillator degraded by 1.5 dB over ten days (240 h) of accelerated stress conditions, and this loss can be recovered by the proposed mitigation scheme.

As promising paths to break the diffraction limit of optical lithography, several self-aligned multiple patterning (SAMP) techniques have been proposed to improve the resolution capability recently. In this paper, we show that SATP (selfaligned triple patterning) process variations differ significantly from conventional optical lithography process. It is found that mandrels fabricated by a SATP process usually come up with worse line-width roughness (LWR) and critical-dimension uniformity (CDU) than spacers do. In addition to that, the gap space between two neighboring spacers is often accompanied with a poor CDU. Similar to SATP process, the self-aligned quadruple patterning (SAQP) technique also brings its own characteristics of process variability along with the scaling capability. SAMP process variability (such as intra-cell variability and process multi-modality) and their impacts on device performance of the multiple-gate MOSFETs are discussed. Moreover, we develop an analytic double-gate MOSFET model to study the effects of LWR on both fin thickness and gate misalignment. Numerical simulations are carried out to verify the accuracy of our simplified model. This analytic approach provides an efficient method for compact modeling of LWR induced device variations.

The shift towards shorter wavelengths in the lithographic process has been the driving force for development of a commercial spectroscopic ellipsometer covering the vacuum ultraviolet (VUV) spectrum. Understanding the optical properties of thin films and substrate materials at short wavelengths (193 nm, 157 nm, and shorter) is necessary to develop the lithographic process. Lithography applications include optical coatings, photoresists, AR films, and masks. We present results for both single and multi-layer structures important to this industry. A complete description of the thin film optical properties can be used to track process changes or variations in sample structure. As an example, we compare the measured index for three oxynitrides that were subjected to different process conditions. In addition to lithography applications, VUV ellipsometry has many other potential applications. A variety of other materials have been characterized, often incorporating generalized ellipsometry to investigate anisotropic optical properties. The ordinary and extraordinary dielectric functions for bulk 4H SiC were measured over the wide spectral range from 0.73 to 8.5 eV.

Due to the low k₁-factor which leads to reduced process latitude, it is becoming increasingly important that OPC and lithography verification take into account process variations. An essential element to the successful implementation of full-chip, process window aware RET/OPC design and verification is a lithography model that is able to accurately describe the lithography process across the entire focus-exposure window. Moreover, a straightforward calibration without requiring excessive amount of through process window measurements is also critical to ensure quick turnaround-time. In this paper, we introduce a new Focus Exposure Matrix (FEM) model based on Brion's Tachyon platform. The FEM model has two adjustable parameters: focus and exposure. By adjusting these parameters, new models at arbitrary process conditions within the process window can be quickly derived, with which large number of simulation results can be obtained at different exposure and focus for detailed process window analysis. The fitting of FEM model is through a single calibration process using wafer measurements at limited number of sampling locations within the process window. The resulting calibrated FEM model is shown to have superior fitting as well as prediction accuracy, without requiring massive additional focus-exposure measurements. Accurate FEM modeling enables two important applications in the deep sub-wavelength regime: lithography manufacturability check (LMC) and optical proximity correction (OPC). FEM-enabled LMC proves to be a substantial advance in model-based verification by providing through process window analysis capability. Furthermore, FEM models can be employed in OPC practically to prevent catastrophic failures due to process variation while still maintaining satisfactory OPC quality in terms of matching the modeled wafer image to design intent. In this paper, we use real data and simulation results to demonstrate the quality of the FEM-model and its effectiveness in the LMC and OPC applications.

For the ion projection lithography space charge experiment [P.W.H. de Jager et al., J. Vac. Sci. Technol. B 17, 3098 (1999)] a suitable stencil test mask has been realized and used. This article addresses the stress engineering and fabrication process of this specific test mask with openings in the range of some few 100 nm up to some 100 μm. This large difference in stencil pattern dimensions causes reactive ion etching (RIE) lag (dependence of the etch rate on feature size and pattern density) during the fabrication process and considerable stress variations across the membrane field. The solution to these problems was by (i) implementing novel doping technologies to create variable thickness areas on the membrane serving as reinforcement and stress relief structures, and (ii) adjusting the design to feature sizes and pattern densities to the same order of magnitude for the e-beam lithography and RIE processing steps. The etching of the openings through the 3 μm thick Si membrane was done by inductively coupled plasma etching with gas chopping techniques. These methods as devoloped for this specific test mask can be used to improve the stencil mask technology in general.

Directed self-assembly (DSA) has the potential to extend scaling for both line/space and hole patterns. DSA has shown the capability for pitch reduction (multiplication), hole shrinks, CD self-healing as well as a pathway towards line edge roughness (LER) and pattern collapse improvement [1-4]. The current challenges for industry adoption are materials maturity, practical process integration, hardware capability, defect reduction and design integration. Tokyo Electron (TEL) has created close collaborations with customers, consortia and material suppliers to address these challenges with the long term goal of robust manufacturability. This paper provides a wide range of DSA demonstrations to accommodate different device applications. In collaboration with IMEC, directed line/space patterns at 12.5 and 14 nm HP are demonstrated with PS-b-PMMA (poly(styrene-b-methylmethacrylate)) using both chemo and grapho-epitaxy process flows. Pre-pattern exposure latitudes of g25% (max) have been demonstrated with 4X directed self-assembly on 300 mm wafers for both the lift off and etch guide chemo-epitaxy process flows. Within TEL's Technology Development Center (TDC), directed selfassembly processes have been applied to holes for both CD shrink and variation reduction. Using a PS-b-PMMA hole shrink process, negative tone developed pre-pattern holes are reduced to below 30 nm with critical dimension uniformity (CDU) of 0.9 nm (3s) and contact edge roughness (CER) of 0.8 nm. To generate higher resolution beyond a PS-b-PMMA system, a high chi material is used to demonstrate 9 nm HP line/ space post-etch patterns. In this paper, TEL presents process solutions for both line/space and hole DSA process integrations.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.