Adaptive Global Elimination Algorithm for Low Power Motion Estimation

This paper presents a new algorithm which outperforms full search block matching algorithm (FSBMA) and other fast search block-matching motion estimation (FBMME) algorithms in terms of improved subjective and objective quality, reduction in computational complexity, increase in speed up factor and low bit rate. Here, unlike FSBMA, a coarse-to-fine search approach is chosen to find the motion vector whereby complexity of motion estimation is greatly reduced. The coarse search sees to that the search will never be caught at a local minimum, as that was the case in many FBMME. The fine search assures the exact location of the global minimum. Pixel sub-sampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. A new evaluation function is introduced which further reduces the computational complexity. Simulation results have proved the effectiveness of the proposed algorithm for low, medium and high motion sequences.

Although advanced motion vector prediction (AMVP) modes based on motion estimation (ME) are selected significantly less due to the merge mode newly adopted in the high-efficiency video coding (HEVC), integer ME (IME) still occupies a large amount of computation in HEVC because the HEVC supports a highly flexible block partitioning structure. Introduction of the merge mode in HEVC substantially affects the optimal search algorithm of IME. Therefore, this gives a chance to reduce the computational complexity of ME with marginal drop of the compression efficiency. This paper proposes a new IME algorithm that significantly reduces its search ranges. Computational complexity of the proposed algorithm is reduced without serious degradation in coding efficiency by obtaining additional accurate motion vector predictors (MVPs) in a bottom-up order and searching narrow regions around multiple MVPs. These bottom-up MVPs are obtained from the prediction units (PUs) in the coding units (CUs) in the hierarchically lower level, which share the pixel area either completely or partially with the current PU. Although the encoder should perform the proposed IME in a bottom-up order from the smallest CUs to the larger CUs, several other processes, such as fractional ME and merges mode are performed in a top-down order to exploit several fast algorithms already adopted in the HEVC test model encoder. To keep compatibility with HEVC standard, the bottom-up MVPs are utilized for only IME. The bitstream is generated using standard AMVP. According to the simulation results, it is confirmed that the proposed algorithm improves the accuracy of MVPs, which leads to the reduction of IME computational complexity up to 81.95% on average with the Bjontegaard delta bitrate of 0.39%.

This paper proposes a motion estimation scheme to reduce the computational complexity of multilayer motion estimation for scalable video coding. Based on the result of the motion estimation of the lower resolution layer referred to as base layer, we developed a new approach for exploring the search range of the enhancement layer with high coding efficiency. This approach is based on the activity defined as the absolute difference between the motion vector predictor and the final motion vector. Based on the correlation of the activities between neighboring layers, an inter-layer activity model was developed using a curve-fitted linear equation to exploit the activity in the base layer for deciding the search center and the search range of the enhancement layer. Each activity pair in the neighboring layers is used to associate the relevant macroblock to one of two groups; boundary region and interior region. The base-layer motion vector predictor is basically selected over all the activity regions; for each activity region, the proposed motion estimation algorithm decides whether to include the median motion vector predictor or not. Minimal sufficient search range is also decided from the inter-layer activity prediction factor that is adjusted to the given sequence. The proposed scheme reduced the execution time of motion estimation by 99.26% at the cost of 1.56% bit-rate increase and 0.048 dB peak signal-to-noise ratio (PSNR) decrease on average compared with the conventional full-search algorithm. The fast full-search block matching algorithm can also be incorporated to obtain the extra CPU time reduction in the motion estimation process. By adopting the fast full-search block matching algorithm (FFSBMA) in JSVM reference software, the CPU time was reduced by up to 91.84% and the memory bandwidth was reduced by 90% at the sacrifice of 1.27% bit-rate increase and 0.041 dB PSNR decrease on average compared with the FFSBMA only.

The complexity of motion estimation in the High Efficiency Video Coding (HEVC) standard is very high as it uses a number of prediction block sizes. The test zonal search (TZS) mechanism is used as motion estimation algorithm in the fast search mode of HM encoder, the reference software for HEVC. In this paper, we present schemes for reducing the complexity of the TZS algorithm for uni-prediction in HEVC. The proposed mechanisms help in reducing complexity of grid, raster and refinement search stages of TZS. The performance of the proposed mechanisms is tested independently and also combined in the fast search mode of HM-16.18. The motion estimation time and the number of search points in the combined algorithm are reduced by 68.14% and 77.10% with a BD-rate of 0.30% and a BD-PSNR of $$-0.007$$ dB in comparison with the original fast search mode in the low-delay P main profile. The proposed complexity reduction schemes are compared with those adopted in other recently proposed fast motion estimation algorithms and the performance of the proposed scheme is found to be superior in terms of the reduction in motion estimation time.

A merging procedure joining search pattern and variable block size motion estimation for H.264/AVC is proposed in this paper. The principal purpose of the proposed methods is the reduction of the computational complexity for block matching module. In fact, there are numerous contributions in the literature aiming the reduction of the computational cost needed for motion estimation. The best solution from a qualitative point of view is the full search that considers every possible detail. The computational effort required is enormous and this makes motion estimation by far the most important computational bottleneck in video coding systems. Our approach invests and exploits the center-biased characteristics of the real world video sequences, aiming to achieve an acceptable image quality while independently targeting the reduction of the computational complexity. The simulations results demonstrated that the proposal performs well.

This dissertation reports on rate-distortion optimized and computation-constrained video coding algorithms which yield effective and efficient block-based video encoders. We first propose a new cost function for motion estimation which can achieve good tradeoffs among motion vector bit rate, compensation distortion, and number of computations. Based on the new cost function, we propose a predictive motion estimation algorithm which can effectively determine the size of the search region according to the statistics of the motion field. The proposed motion estimation algorithm allows control of the motion vector bit rate and the computational cost, simultaneously. We also develop two efficient rate-distortion optimized coding mode selection algorithms, based on thresholding and finite state machine (FSM) methods, respectively. The thresholding method can eliminate consideration of the computationally expensive modes. The FSM method determines the test orders of the modes and associated parameters by exploiting the local statistics of the input video sequence. The proposed two methods can reduce substantially the computation requirements as compared to the full search mode selection method. Based on the proposed motion estimation and mode selection algorithms, we implement an H.263-based video coder and an MPEG-2, compliant video coder for very low bit rate video applications, and high bit rate interlaced video applications, respectively. The resulting video coders achieve excellent tradeoffs among bit rate, quality, and computational complexity. In fact, experimental results show that our video coders outperform the best known video coders in terms of compression performance and encoding speed.

Block sizes larger than the traditional 16×16 macroblock (MB) structure and extended macroblock (EMB) size motion estimation (ME) are introduced in joint model key technology areas software to improve the inter block coding efficiency. Similar to H.264, variable size motion estimation (VS-ME) is still adopted for each 16×16 MB including 16×16, 16×8, 8×16, 8×8, 8×4, 4×8, and 4×4. EMB size ME and VS-ME achieve the highest possible coding efficiency, but result in extremely large coding time which obstructs it from practical use. A fast mode decision algorithm for EMBs based on motion homogeneity is proposed to reduce the computational complexity of ME. The basic idea of the proposed method is to utilize the spatial property of motion field in prediction where EMB size ME and small size ME (including 8×8, 8×4, 4×8 and 4×4) are needed, and only in these regions EMB size ME and small size ME are enabled. The motion field is generated by the corresponding motion vectors in spatial window. Simulation results show that the proposed algorithm can save 55% average computational complexity, with negligible loss of coding efficiency.

The recent video compression standard, HEVC (high efficiency video coding), will most likely be used in various applications in the near future. However, the encoding process is far too slow for real-time applications. At the same time, computing capabilities of GPUs (graphics processing units) have become more powerful in these days. In this paper, we have proposed a GPU-based parallel motion estimation (ME) algorithm to enhance the performance of an HEVC encoder. A frame is partitioned into two subframes for pipelined execution to improve GPU utilization. The flow chart is redetermined to solve data hazards in the pipelined execution. Two new methods are introduced in the proposed ME: decision of a representative search center position (RSCP) and warp-based concurrent parallel reduction (WCPR). A RSCP employs motion vectors of a co-located CTU in a previously encoded frame to solve a dependency problem in parallel computation with negligible coding loss. WCPR concurrently executes several parallel reduction operations, which increases the thread utilization from 20 to 89 % without any thread synchronization. The proposed encoder can make the portion of ME in the encoder negligible with 2.2 % bitrate increase against the HEVC test model (HM) encoder. In terms of ME, the proposed ME is 130.7 times faster than that of the HM encoder.

The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity in the video encoder. This high consumption of the computational resources puts a limit on the performance of encoders, especially for full HD or ultra HD videos, in terms of coding speed, bit-rate and video quality. Thus the major part of this work concentrates on the computational complexity reduction and improvement of timing performance of motion estimation algorithms for HEVC standard. First, a new strategy to calculate the SAD (Sum of Absolute Difference) for motion estimation is designed based on the statistics on property of pixel data of video sequences. This statistics demonstrates the size relationship between the sum of two sets of pixels has a determined connection with the distribution of the size relationship between individual pixels from the two sets. Taking the advantage of this observation, only a small proportion of pixels is necessary to be involved in the SAD calculation. Simulations show that the amount of computations required in the full search algorithm is reduced by about 58% on average and up to 70% in the best case. Secondly, from the scope of parallelization an enhanced TZ search for HEVC is proposed using novel schemes of multiple MVPs (motion vector predictor) and shared MVP. Specifically, resorting to multiple MVPs the initial search process is performed in parallel at multiple search centers, and the ME processing engine for PUs within one CU are parallelized based on the MVP sharing scheme on CU (coding unit) level. Moreover, the SAD module for ME engine is also parallelly implemented for PU size of 32×32. Experiments indicate it achieves an appreciable improvement on the throughput and coding efficiency of the HEVC video encoder. In addition, the other part of this thesis is contributed to the VLSI architecture design for finding the first W maximum/minimum values targeting towards high speed and low hardware cost. The architecture based on the novel bit-wise AND scheme has only half of the area of the best reference solution and its critical path delay is comparable with other implementations. While the FPCG (full parallel comparison grid) architecture, which utilizes the optimized comparator-based structure, achieves 3.6 times faster on average on the speed and even 5.2 times faster at best comparing with the reference architectures. Finally the architecture using the partial sorting strategy reaches a good balance on the timing performance and area, which has a slightly lower or comparable speed with FPCG architecture and a acceptable hardware cost

In this paper, we propose a fast block motion estimation scheme by exploiting the correlations of motion vectors (MV) existing in spatially- and temporally-adjacent as well as hierarchically-related blocks. The basic idea is to use the information obtained from the corresponding block at a coarser resolution level and spatio-temporal neighboring blocks at the same level in order to select a good set of initial MV candidates and then perform further local search to find the best matching MV. In order to further reduce computational complexity, the sign pattern vector (SPV) is defined and used for block matching, as opposed to the pixel intensity values used in the conventional block matching methods. By using the SPV definition, a data block can be presented by a mean and a set of binary sign patterns with a much reduced data set. The block matching motion estimation is then divided into mean matching and binary phase matching. The proposed technique enables a significant reduction in computational complexity compared with the conventional block matching motion estimation (ME) because binary phase matching only involves Boolean logic operations. This scheme also significantly reduces the data transfer time between the frame buffer and motion estimator. Our test results indicate that the performance of the proposed scheme is comparable with the full-search block matching under the same search ranges, however, the proposed scheme has a speed-up factor ranging from 250 to 370 in comparison with full search.

SVD-based redundancy removal in 1-D CNNs for acoustic scene classification

The constrained two-bit transform (C2BT) is recently proposed for low complexity motion estimation (ME) to reduce the high computational complexity of the typical two-bit transform (2BT) while maintaining the ME accuracy. And the bit-inverted Gray-coded bit-plane matching (BGCBPM) is also proposed to enhance the ME accuracy. In this paper, we propose a fast ME algorithm exploiting these two bit-plane matching (BPM) criteria. Using the low complexity image transformations of typical images into bit-planes and their corresponding matching criteria and another hybrid matching criterion, we can efficiently determine multiple candidate motion vectors and increase the ME accuracy substantially. Experimental results show that the peak-to-peak signal-to-noise ratio (PSNR) difference between the proposed algorithm and the typical sum of absolute differences (SAD) based full search algorithm is only 0.03 dB on average with negligible computational complexity increase.

Previous studies show that the motion vector distribution within the search window shows a center biased behavior. Based on this fact, an advanced center biased search algorithm for fast block motion estimation has been proposed. The algorithm drastically reduces the computational complexity by strict application of the unimodal error surface assumption. Improved error performance has been achieved by an efficient center biased search strategy that improves the chances of getting the correct motion vector. The half stop technique has been adopted to speed up the block matching process. Experimental results show that proposed algorithm has improved performance as compared to the three step search algorithm. A good predicted image quality is also achieved.

Motion estimation (ME) has the highest computational complexity in motion-compensated frame rate up-conversion (MC-FRUC). For the real-time implementation of FRUC, a fast ME algorithm is required. In this paper, a new hierarchical ME algorithm for MC-FRUC is proposed. It constructs an image pyramid by dividing the frame into several sub-images according to resolution, and performs ME at the top level to reduce complexity while improving accuracy by selecting multiple motion vector candidates. These candidates are refined at the lower levels, and the final motion vector is selected at the bottom level. Thus, the proposed algorithm obtains an average peak signal-to-noise ratio gain of upto 0.85 dB compared to conventional algorithms with lower computational complexity and yields interpolated images with better visual quality than other methods.

H.264/AVC the latest international video coding standard achieves higher compression efficiency than previous video coding standards such as MPEG-4 and H.263. However, this performance gain comes at the cost of an increased computational complexity. To achieve a high coding efficiency, H.264/AVC employs complex mode decision techniques based on Rate Distortion Optimization, the computational complexity is very high[1]. This is a major bottleneck for the H.264/AVC in real-time application. Inter-frame prediction coding is a more important part in H.264/AVC. In order to reduce the computational complexity, a fast mode decision algorithm is proposed for Inter-frame in H.264/AVC video coding standard in this paper. With the new algorithm, the amount of computation involved in the motion estimation and mode decision can be substantially reduced. Simulation results show that the proposed algorithm can reduce 56.52% on average of the total encoding time, with a slight increase in bit rate and a negligible PSNR drop.