1- https://doi.org/10.1007/978-1-4419-9692-3_5
Adaptive Low-power Reconfigurable Processor Architecture
- Jan 1, 2011
- Muhammad Shafique +1 more
This chapter presents the novel adaptive low-power reconfigurable processor architecture with a run-time adaptive energy management scheme. It exploits the novel concept of Selective Instruction Set Muting with multiple muting modes. The first section analyzes different scenarios, while motivating the need for run-time energy management. Afterwards, the adaptive energy management scheme with the novel concept of Custom Instruction (CI) Set Muting is discussed in Sect. 5.2. In this section different CI muting modes are explained along with the corresponding configuration of sleep transistors for different parts of the reconfigurable fabric. Afterwards, the required power-shutdown infrastructure is discussed. In Sect. 5.2.3 an overview of the energy management scheme is provided highlighting different requirements and steps considered at design-, compile-, and run-time.
- # Custom Instruction
- # Run-time Energy Management
- # Run-time Energy
- # Energy Management Scheme
- # Run-time Management
- # Custom Instruction Set
- # Adaptive Management
- # Instruction Set
- # Adaptive Scheme
- # Configuration Of Transistors
