Adaptive Non-Uniform Compressive Sensing Using SOT-MRAM Multi-Bit Precision Crossbar Arrays

Convolutional Neural Network (CNN) is one of the most important Deep Neural Networks (DNN) classes that helps solving many tasks related to image recognition and computer vision. Their classical implementations by using conventional CMOS technologies and digital design techniques are still considered very energy-consuming. Floating point CNN relies primarily on MAC (Multiply and ACcumulate) operation. Recently, cost-effective Bite-wise CNN based on XNOR and bit-counting operations have been considered as a possible hardware implementation candidate. However, the Von-Neumann bottleneck due to intensive data fetching between memory and the computing core limits their scalability on hardware. XNOR-BITCOUNT operations can be easily implemented by using In Memory Computing (IMC) paradigms executed on a memristive crossbar array. Among emerging memristive devices, the Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) offers the possibility to have a higher ON resistance that allows reducing the reading current, since all the crossbar array is read in parallel. This could contribute to a further reduction of energy consumption, paving the way for much bigger crossbar designs. This study presents a crossbar architecture based on SOT-MRAM with very low energy consumption; we study the impact of process variability on the synaptic weights and perform Monte-Carlo simulations of the overall crossbar array to evaluate the error rate. Simulation results show that this implementation has lower energy consumption with respect to other memristive solutions with 65.89 fJ per read operation. The design is also quite robust to process variations, with very low reading inaccuracies up to 10 %.

This paper presents a spin-orbit torque magnetic random access memory (SOT-MRAM) using perpendicular-anisotropy magnetic tunnel junction (p-MTJ). In spite of conventional p-MTJ based SOT-MRAMs which need an external magnetic field to achieve a deterministic switching, the proposed cell uses a spin-torque transfer (STT) current where we show that the cell needs only two access transistors. This can solve the thermal instability, complexity and process variation sensitivity issues of the conventional SOT-MRAMs. In addition, it maintains the advantage of conventional p-MTJ based SOT-MRAMs such as ultra-fast switching and enhanced reliability of the MTJ. Our simulation results show that the proposed SOT-MRAM can achieve 3.3X and 2.8X faster and energy efficient write operation in comparison with the conventional SOT-MRAMs.

Due to the leakage power of CMOS-based memory, Nonvolatile magnetic memory is considered a strong candidate to replace the CMOS-based memory. Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising candidates, but it still has many shortcomings related to the write operation. Compared to STT-MRAM, spin orbit torque magnetic random access memory (SOT-MRAM) is the next generation of nonvolatile magnetic memory because of its relatively good performance and low power. Although SOT-MRAM has various advantages over STT-MRAM, a significant reduction in write power is required to meet the power level of CMOS-based memory. In this paper, we present a low power SOT-MRAM cell configuration using the dual write operation. By writing on two cells simultaneously, write energy can be reduced depending on data patterns. Compared to the conventional 2T-1MTJ SOT-MRAM, the proposed SOT-MRAM cell with the dual write scheme reduces the write energy by 26.3% on average.

As an emerging non-volatile memory technology, the spin orbit torque magnetic random access memory (SOT-MRAM) has attracted intensive research interest due to its advanced performance. However, the binary storage feature of the SOT-MRAM has become one of the obstacles. In this paper, we present a study of two-bit multi-level SOT-MRAM where two canted in-plane-anisotropy magnetic tunnel junctions (MTJs) store a pair of data. Compared with the previous schemes of multi-level SOT-MRAMs, our proposal enables fully one-step writing without the need of the preset operation. Micromagnetic simulation is performed to validate the functionality of the proposed multi-level cell (MLC) SOT-MRAM, meanwhile, the details of magnetization switching are clearly shown. Simulation results also demonstrate that the device could accomplish the magnetization switching at the sub-nanosecond speed and continuously decreasing power consumption with the size scaling down. In addition, the dipolar field between two cells has little influence on the switching process.

This paper presents a multilevel spin-orbit torque magnetic random access memory (SOT-MRAM). The conventional SOT-MRAMs enables a reliable and energy efficient write operation. However, these cells require two access transistors per cell, hence the efficiency of the SOT-MRAMs can be questioned in high-density memory application. To deal with this obstacle, we propose a multilevel cell which stores two bits per memory cell. In addition, we propose a novel sensing scheme to read out the stored data in the multilevel SOT-MRAM cell. Our simulation results show that the proposed cell can achieve 3X more energy efficient write operation in comparison with the conventional STT-MRAMs. In addition, the proposed cell store two bits without any area penalty in comparison to the conventional one bit SOT-MRAM cells.

As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-the-art SOT-MRAM-based LUT.

Resonance spin-transfer torque in ferromagnetic/normal-metal/ferromagnetic spin-valve structure of topological insulators

Spin-transfer torque magnetic random access memory devices (STT-MRAMs) show great promise as a candidate technology for on-chip caches. In this letter, we propose a new STT-MRAM bit-cell structure that is suitable for on-chip caches compared with the standard STT-MRAM bit-cell (SSC). Scalability of our proposed structure is studied with the aid of micromagnetic and circuit simulators. Results show that our proposed bit-cell is more scalable than the SSC, achieving>; 4× better write margin, >; 65% better sensing margin, lower read disturb failures, and subnanosecond sensing delays.

Spin-transfer magnetic random access memory (MRAM) devices with a polarizing layer magnetized perpendicular to the free and the reference layers are believed to improve the writing performance by inducing a large spin-transfer torque on the free layer at the beginning of the switching process. Experimental realizations of such devices, both with all-metal structures and magnetic tunnel junctions have been made. Faster switching with less energy cost in the orthogonal devices has been achieved comparing to their collinear counterparts. In addition, the processional switching process in such devices has been demonstrated in both statistical and time-resolved measurements. Although further theoretical and material studies are needed for thorough understanding of the switching process and improving the device performance, the orthogonal MRAM devices hold great potential for memory applications operating at low temperatures as well as those that require fast writing speed.

The non-volatile spin–orbit torque magnetic random access memory (SOT-MRAM) is a very attractive memory technology for near future computers because it has various advantages such as non-volatility, high density and scalability. In the present work we propose a model of a graphene recording device for the SOT-MRAM unit cell, consisting of a quasi-freestanding graphene intercalated with Au and an ultra-thin Pt layer sandwiched between graphene and a magnetic tunnel junction. As a result of using the claimed graphene recording memory element, a faster operation and lower energy consumption will be achieved under the recording information by reducing the electric current required to record. The efficiency of the graphene recording element was confirmed by the experimental results and the theoretical estimations.

The steady increase in performance and speed of modern integrated circuits is continuously supported by constant miniaturization of complementary metal-oxide semiconductor devices. However, the rapid growth of the dynamic and stand-by power due to transistor leakages becomes a pressing issue. A promising way to interrupt this trend is to introduce non-volatility. The development of an electrically addressable non-volatile memory combining high speed and high endurance is essential for achieving these goals. The perpendicular spin-orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is thus suitable for applications in caches. However, its development is still hindered by the necessity of a static in-plane magnetic field. We propose a magnetic field-free perpendicular SOT-MRAM, operated by two consecutive perpendicular current pulses, which is fast and, most importantly, does not require an external magnetic field.

Back-hopping type soft errors and etching-induced shunting failure are among the primary failure mechanisms preventing spin-orbit torque magnetic random access memory (SOT-MRAM) technology from commercialization. In this work, a novel writing scheme is proposed, which effectively suppresses back-hopping type soft failures, achieving a writing error rate below 1 ppm and a significantly widened write margin for enhanced reliability. Meanwhile, by inserting a buffer layer between the free layer and the SOT layer, we demonstrated significantly reduced shunting failure, yield improvement, and a raw bit error rate down to 52 ppm on 300 mm wafers. Additionally, a high-yield magnetic tunnel junction with a tunnel magnetoresistance (TMR) of 134% is demonstrated through material and stack optimization. These progresses pave the way for the development of high-density SOT-MRAM chips with Mbit~Gbit capacities.

In spin–orbit torque magnetic random access memory (SOT-MRAM), as write energy is much larger than read energy, writing data to memory only when the new data is different from the stored data can lead to considerable write energy savings. In this paper, we propose three low-power techniques that can significantly reduce write energy in the read–compare–write process. In the proposed approaches, redundant charge in read operation has been efficiently reused to generate a negative voltage for write assistance, which leads to short write time. A selective precharging technique is also proposed to minimize the voltage swings between read and write operations. In addition, asymmetric write current due to source degeneration of write transistor can be resolved with the write voltage suppression scheme. Our circuit simulations with 65-nm CMOS technology show that when the stored data and new data are the same, up to 61% of write energy savings have been achieved compared with the conventional 2T-1MTJ cell. When the proposed SOT-MRAM is used as L3 caches of X86 processor, the gem5 simulations also show that average 48.2% of write energy savings can be achieved in various workloads of SPEC2006.

To make spin–orbit torque magnetic random access memory (SOT-MRAM) practical, current-induced magnetization switching without an external bias field is essential. Given that the CoFeB/MgO structure has already been used in typical spin-transfer torque-MRAM for its high tunneling magnetoresistance, leveraging a similar material system to achieve field-free SOT switching is of great importance. In this work, we systematically investigate the field-free switching mechanism in CoFeB/W/CoFeB T-type structures, where the two CoFeB layers are in-plane and perpendicularly magnetized, respectively. Initial SOT characterization shows a sizable zero-field SOT efficacy (χHx=0) for such T-type devices. Furthermore, field-free angle-dependent SOT measurement confirms the parallel relationship between the built-in bias field and the magnetization of the in-plane magnetized CoFeB. Based on thorough verification and exclusion of other potential mechanisms, the Néel orange-peel effect emerges as the dominant origin for such a built-in bias field, where a positive correlation between the deposited film surface roughness and χHx=0 is found. Based on this discovery, the field-free switching efficacy in T-type structures is further optimized via film roughness tuning and examined with pillar-shaped devices. Our results provide insights into the tentative approach to improve field-free switching using T-type devices and the feasibility of downscaling.

Deep Convolutional Neural Networks (CNNs) are widely employed in modern AI systems due to their unprecedented accuracy in object recognition and detection. However, it has been proven that the main bottleneck to improve large scale deep CNN based hardware implementation performance is massive data communication between processing units and off-chip memory. In this paper, we pave a way towards novel concept of in-memory convolver (IMC) that could implement the dominant convolution computation within main memory based on our proposed Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array architecture to greatly reduce data communication and thus accelerate Binary CNN (BCNN). The proposed architecture could simultaneously work as non-volatile memory and a reconfigurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in conventional logic-in-memory designs. The computed logic output could be also simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. We employ such intrinsic in-memory processing architecture to efficiently process data within memory to greatly reduce power-hungry and long distance data communication concerning state-of-the-art BCNN hardware. The hardware mapping results show that IMC can process the Binarized AlexNet on ImageNet data-set favorably with 134.27 μJ/img where ∼ 16x and 9x lower energy and area are achieved, respectively, compared to RRAM-based BCNN. Furthermore, 21.5% reduction in data movement in term of main memory accesses is observed compared to CPU/DRAM baseline.