Adaptive slope compensation for high bandwidth digital current mode controller

It is excessive or insufficient slope compensation current in buck DC-DC converters that cause available load current reduction and subharmonic oscillation issues. In this paper, a slope compensation circuit scheme was proposed, concerned with the input/output voltage changes and the product of the inductor current and the on-resistance of the power transistor. Compared with the traditional adaptive slope compensation circuit, the proposed circuit includes the influence factor of the power transistor on-resistance and demonstrates its slope compensation relationship, based on which an adaptive slope compensation circuit with Flip Voltage Fllower (FVF) structure is formed. Finally, the self-regulation and precise controlling of compensation amount can be achieved. The load capability and transient response of the DC-DC converter is improved and thus the system stability can be guaranteed. Experimental results show that the maximum inductor current change is less than 12% with the duty cycle ranging from 11% to 73%.

This study proposes the application of valley current mode (VCM) control in a flyback dc–dc converter with a large duty cycle. The use of VCM control eliminates the need of slope compensation in operation under a duty cycle greater than 50%. For operation with duty cycle near the boundary value (50%), a relatively small compensation ramp is required comparing with that of the conventional peak current mode (PCM) control. Moreover, the noise sensitivity issue of PCM control is also addressed by the change of the current sensing position in VCM and hence the immunity against the current spike. The VCM-controlled flyback converter achieves consistent steady-state and transient-response performances as its PCM-controlled counterpart. Stability analyses of inner current loop and overall closed-loop system are presented. Experiments are also conducted to evaluate the effectiveness of VCM control in controlling the flyback dc–dc converter.

This paper presents a 100-kV high frequency transformer/rectifier package, which is capable of a dual output polarity operation. An H-Bridge inverter drives the primary of the high voltage (HV) transformer at a frequency of 20 kHz. The inverter is driven by a Microchip dsPIC33F digital signal controller using peak current mode control with adaptive slope compensation. The HV-tank has two HV-coax output cables with a grounded shield on each cable. If the center conductor of the coax cable designated as negative output is grounded, positive voltage is obtained from the coax cable designated as positive output and vice versa. This paper provides design details and experimental results from tests of the entire system.

Digital current mode control finds wide spread application in point of load power converters in DC nano-grid because of its technical benefits. However, finite current-loop sampling effects introduce undesirable sub-harmonic oscillations. This paper presents an analytical framework to investigate such nonlinear phenomena in a digitally current mode controlled boost converter. Discrete-time models for multi-sampled current loops and uniform sample with compensating ramp are derived under continuous conduction mode. We show that the discrete-time maps for such systems are discontinuous in nature. While the error voltage using a proportional-integral controller stays within the zero-error-bin (ZEB), the reference current becomes constant and 1-D maps of the inner current-loop can be used for stability analysis. Uniform sampling may lead to chaos, period doubling or stable period-1 behavior depending on slope of the compensating ramp. Multi-sampled current loop imposes several borders in the discrete parameter space and may eventually lead to high periodic behavior. In a counter-based compensating ramp, staircase effects may lead to sub-harmonic oscillation. Such instability eventually brings the error voltage outside the ZEB and 2-D map models have to be used for further investigating the nonlinear phenomena. A boost converter prototype was made. Digital current mode control is realized using an FPGA device. Test results demonstrate close agreement with the analysis.

High step-up gain Coupled Inductor Boost Converter (CIBC) discovers application in Distributed Generation System (DGS) to step-up voltage level of renewable energy sources. In DGS system, high step-up CIBC with a regulated output voltage and faster dynamic operation is required at various local loads. Transfer function of CIBC has one zero on Right Hand Plane (RHP). It is difficult to achieve high bandwidth when system has Non-Minimum Phase (NMP) characteristic. Peak Current Mode (PCM) control is the well-known technique to improve dynamic response in DC-DC converters. To design feedback controller and to analysis behaviour of CIBC, small signal model of CIBC is required. This paper presents small signal control-to-output voltage transfer function for PCM control of CIBC. Effect of artificial ramp is considered in derivation of this small signal model. A state space averaging method is used to derive small signal model. PI controller is designed using root locus technique. Time and frequency response of Voltage Mode Control (VMC) and PCM control of CIBC are compared. PCM control improves transient response and stability margin of CIBC for wide range of load variations. It also reduces effect of RHP zero. Simulation of CIBC using PCM control to get regulated output voltage is done in PSIM. Simulation results demonstrate that CIBC is able to get desire dynamic and steady state response of output voltage using PCM control under dynamic load conditions.

A monolithic high-performance step-down dc–dc converter for high power point-of-load application is presented in this paper. A novel adaptive quadratic slope compensation method and an adaptive antijittering ramp scheme are proposed to enhance the performance of widely used peak current-mode control. A fast overcurrent detection method together with a robust driver control logic design has been introduced to increase the circuits' reliability. The dc–dc converter has been designed and fabricated in a 0.35-μm Bipolar-CMOS-DMOS process with an area of 6 mm2. With the proposed enhanced current-mode control, our design allows more flexibility on inductor selection, switching frequency, and output voltage. Experimental results have shown great adaptability for various application configurations. This converter has also shown fast line step response and low PWM jittering. It can operate at beyond 9-A peak current and up to 1.4-MHz switching frequency with supply voltage from 2.35 to 6 V. Measured peak efficiency is 96.6% and over 92% efficiency for 6-A output current is realized as well.

This paper presents a unified discrete model for pulse-width modulated (PWM) switching DC to DC converters. The major achievement is that, without any topology modification, the proposed model can be used for performance analysis of the buck, boost and buck-boost converters with any of the two current-mode controls: peak current-mode control and average current-mode control. Three important factors are considered: parasitical effects of circuit elements, non-linear inductance dependent on the current flowing through it, and control time delay, such that the accuracy of performance prediction is greatly improved. Magnetic field finite element analysis (FEA) is conducted to calculate the non-linear differential inductance. By implementing the proposed model into Matlab/Simulink, a simulation model is built. The model has been used for the performance analysis of an existing flyback converter with the peak current-mode control. The simulation results are in good agreement with the actual performance, validating the proposed model.

General equation for the control current for the inner-current loop of pulse-width modulated (PWM) dc–dc power converters with peak current-mode control without slope compensation is derived. Derivations of expressions for the control current as functions of duty cycle and phase margin at power stage specifications for buck, boost and buck–boost dc–dc converters in continuous conduction mode (CCM) are presented. Relative stability of the inner-current loop without slope compensation was analysed. Experimental and Saber simulation results for a buck converter with the inner-current loop are presented to validate the theory presented. The results obtained can be used to determine the range of control voltage required by the inner loop, to select a proper value of sense resistance, and to design the control circuit in the outer-voltage loop of peak current-mode controlled PWM DC–DC converters. It is shown that the phase margin of the inner loop is 0° at a duty cycle value of 0.5 and increases as the duty cycle decreases.

This paper represents the digital current mode control for a multi-module bidirectional converter intended for battery charging/discharging applications. The digital current mode control is adapted to achieve equal current sharing and good dynamic performance. The predictive control is used for the digital current compensation and the direct method is adapted to the digital voltage compensation. The control parameters for the digital compensations are designed and fine-tuned using the SISO tool in MATLAB software. Theoretical predictions are confirmed with both MATLAB simulations and measurements on an experimental prototype converter.

An adaptive control technique for a digital current mode control of dc-dc converters is proposed in this paper. The adaptive digital controller is designed to maintain the optimum gain-phase of the outer control loop regardless of the changes in the load value. In the control algorithm, the load resistance is calculated using the average current and output voltage values inside the digital processor. Next the calculated value of the load resistance is used to tune the Proportional-Integral (PI) controller such that the requirements for crossover frequency and phase margin values are fulfilled. In order to avoid the calculation burden to slow down the program execution speed, the parameter values of PI controller for each value of the load resistance are inserted into a look-up table inside the digital processor. To verify the proposed technique, the controller is implemented in an FPGA to control a buck converter. The experimental results show the excellent performance of the controller in presence of a load change.

This paper presents the disturbance rejection of peak current-mode control for bidirectional Buck-Boost converter using slope compensation. The equivalent circuits and transfer functions are derived for the peak-current mode control using small signal modeling. In order to utilize the benefits of peak current-mode controller and eliminate its drawbacks, slope compensation has been added. The derived transfer functions help to analyze the stability of the controller and current disturbance rejection. Bode plots of the current transfer functions are extracted to analyze the correct behavior of the controller and compare the results for different perturbation ratio under various slope compensations. The detailed stability analysis leads to design criteria and choose appropriate parameters for the robust disturbance-rejection control.

ABSTRACTWith the rapid development of automotive infotainment, industrial DC‐DC motors and telecom servers, the demand for buck converters with high‐input or wide‐input voltage is increased. This paper proposes a synchronous buck converter with a wide input voltage range, utilizing a simulated peak current mode. The proposed simulated peak current control mode removes the need for a separate slope compensation circuit. By integrating a slope compensation current directly into the ramp generator, it eliminates subharmonic oscillation issues when the duty cycle in current mode control exceeds 50%, thereby simplifying circuit design. The proposed simulated peak current mode retains the key advantages of peak current mode, such as feedforward control, easy overcurrent protection, and easy loop compensation, while significantly enhancing the loop's immunity to interference. This enhancement reduces the noise sensitivity of the pulse width modulation circuit, eliminates false switch turn‐offs caused by leading‐edge spikes, and removes the need for external low‐pass filters. Furthermore, with the integration of high‐voltage regulation technology, it achieves a wide input–output range, broadening its application scope. As a result, the proposed mode is more robust and reliable in applications with high stability and anti‐interference requirements, such as automotive infotainment, industrial DC–DC motors, and telecom servers, offering strong support for reliable and precise power system performance. The proposed converter is implemented using UMC 250 nm BCD technology and operated at a frequency range of 50 kHz–1 MHz, with the maximum output current up to 7 A, a wide input voltage range of 6–100 V, and an output voltage range of 1.215–80 V. Besides, excellent minimum ripple/output ratio (0.0325%) and maximum power efficiency (90.93%) are achieved.

Peak current mode (PCM) control has been widely used for the control of switching dc–dc converters due to its excellent transient performance. With the development of single-inductor dual-output (SIDO) dc–dc converters, PCM control technique is introduced to the control of SIDO dc–dc converters. Conventional PCM buck converter has only one reference current, with two inductor current borderlines are used to divide the operation modes of inductor current. However, PCM SIDO buck converter has more inductor current borderlines as it has one more reference current than that of PCM buck converter. In this paper, inductor current borderlines of PCM SIDO buck converter are investigated, and unified discrete iterative model of PCM SIDO buck converter is established. The effect of the difference of reference currents, initial inductor current and input voltage on the stability of PCM SIDO buck converter has been discussed by using bifurcation diagrams. The study results show that the stability of PCM SIDO buck converter is sensitive to the difference of reference currents, initial inductor current and input voltage. The stability boundary of the difference of reference currents, stability region of initial inductor current, and stability boundary of input voltage are derived. Lyapunov exponent and experimental results are carried out to verify the theoretical analysis results.

In this paper, average current mode control and peak current mode control methods are compared. A full-bridge converter has been chosen to test the controller performances. For the accurate design of controllers, some performance parameters are specified for the converter. The full-bridge converter output is used as 28V, 5.6kW. The desired maximum ripple at the output voltage is 200mV and the allowable ripple at the output current is 5A. Converter performance has been simulated with PSIM and discussed. Then, average current mode controller and peak current mode controller designs were made with this converter. The design of these methods has been done separately and has been simulated. Comparative results of these controllers were given and their pros and cons over each other were discussed. The things to be done to make the performance improvements of the controllers were mentioned and evaluated.

Stability of a distributed power architecture (DPA) still remains a major concern, even though individual stand-alone DC-DC converters are designed with sufficient (small-signal) stability margins. In such architectures, a tightly regulated point-of-load (PoL) converter resembles a constant power load (CPL) which introduces a negative-impedance effect to the source converter. This effect may introduce limit cycle oscillation (LCO) and may eventually destabilize the overall DPA. In this paper, a source buck converter is considered under digital current-mode control (DCMC) with a proportional-integral (PI) voltage controller, which is driving a CPL buck converter. During a power step-transient in the CPL, stable controller gain ranges under DCMC are computed for the source converter for individual operating conditions. Thereafter, a phase-plane based geometric framework is proposed to compute the optimal proportional gain for the source converter to achieve near time optimal recovery. A hardware prototype is made with 50 W nominal power ratings for individual converters. Analytical predictions and improved performance are validated experimentally.