Adaptive Zero-Sequence Voltage Injection for Modular Solid-State Transformer to Compensate for Asymmetrical Fault Conditions

Modular multilevel converter (MMC) is drawing more and more attention in medium-voltage microgrid applications. Large-scale switching-off loads and grid faults may lead to the voltage swell in microgrid, where MMC should have the ride-through ability. In this paper, a simple operation approach with the fundamental and irregular zero-sequence voltage (ZSV) injection is proposed for MMC under grid voltage swell condition. First, the fundamental ZSV injection is applied to adjust the modulation margin of three phases where the amplitude values of modulation waves in each phase can be the same. Then, if the amplitudes with fundamental ZSV injection are still in over-modulation status, the new irregular ZSV injection is added to further enlarge the operation region. In addition, the limitation of the irregular ZSV injection is analyzed. Simulation and experimental results of MMC under different grid voltage swell conditions verify the effectiveness of the proposed operation approach.

Thermal stresses induced by high root-mean-square (rms) currents in dc-link capacitors significantly affect their lifetimes and compromise the overall reliability of converter systems. This article proposes a novel zero-sequence voltage (ZSV) injection method to reduce the rms current in dc-link capacitors for back-to-back three-level converters. The proposed method adjusts the overlapping intervals of dc bus currents by injecting a differential ZSV on either the rectifier or inverter side, while a common ZSV is injected on both sides to control the neutral point voltage. Simulation and experimental results demonstrate that the proposed method reduces the capacitor rms current by up to 40%–50%, with minimal effect on the total harmonic distortion of the output currents. The proposed method improves system reliability by reducing power losses in the capacitors and extending their operational lifetimes, making it highly suitable for applications that demand both high efficiency and reliability.

High frequency and high amplitude common-mode voltage (CMV) can induce a number of problems on the reliable operations of back-to-back two-level converters, such as shaft voltages and bearing currents. To restrain the CMV for back-to-back two-level converters, a simple and effective CMV reduction method based on zero-sequence voltage (ZSV) injection is proposed in this article. By injecting the optimal amount of ZSV on either the rectifier-side or the inverter-side, the corresponding pulse overlapping areas that result in high CMV amplitudes can be eliminated with the proposed method, then the amplitude of CMV can be reduced by half, and the pulse edges of CMV can be reduced by one-third. Simulation and experimental results are presented to verify the effectiveness of the proposed method in CMV reduction, while some comparisons are also conducted to demonstrate the superiority of the proposed method.

Hybrid transmission systems associated with line commutated converters (LLC) and voltage source converters (VSC) have gradually become a particular solution for high voltage direct current (HVDC) transmission. The full-bridge submodule (FBSM) based modular multilevel converter (FB-MMC) has gained significant attention for its dc voltage reversal and fault ride through capabilities. However, large capacitance is essential for high power transmission of FB-MMC, increasing cost and size rapidly. This paper analyzes the FBSM voltage fundamental frequency and second-order harmonic fluctuations of the FB-MMC with zero sequence voltage injection. The design principles of the FBSM capacitance are also presented compared with the one without zero sequence voltage injection under equivalent voltage ripple conditions. Finally, comparative simulation results on a FB-MMC system verify the correctness of the analyses.

Currently, the grid-tied guidelines all require large and medium-sized photovoltaic (PV) power stations to stay connected to the grid during low-voltage ride through (LVRT). However, three-phase cascaded PV solid-state transformer (SST) has the inherent active power backflow problem during asymmetric voltage sags, causing that H-bridge dc-bus voltages are out of control and that the converter will be disconnected from the grid because of overvoltage fault. The existing control strategy is capable of avoiding active power backflow in theory by injecting appropriate zero-sequence voltage, but the overmodulation range is larger during interphase short-circuit fault, weakening active power backflow suppression effect. For this issue, this article proposes a combined control method of positive–negative-sequence maximum–minimum harmonic zero-sequence voltage injection strategy and adaptive zero-sequence voltage compensation strategy, which can shrink effectively active power backflow range of three-phase cascaded PV SST, increasing its adaptability to different output powers and different grid drop depths, and then improving LVRT capability of the PV power generation system. Finally, a low-voltage and low-power experimental prototype is made to verify the effectiveness and feasibility of the proposed control strategy.

This paper proposes an inter-cluster balancing of an input-parallel output-series modular multilevel cascaded solid-state transformer (SST) based on a feedforward negative-sequence power control. An imbalanced energy flow into each cell of the SST would cause the dc-capacitor voltage of each cell to diverge if the outflow of energy were not regulated to be equal to its inflow. The proposed method distributes the DC-input power to the three clusters corresponding to the AC output power imbalance among the three clusters. This enables the SST to prevent the divergence of the dc-capacitor voltage of each cell without the zero-sequence voltage injection. Simulation results are presented to validate the effectiveness of the proposed control.

Cascaded H-bridge converter is a promising candidate for large scale grid connected solar PV plant. However, non-uniform power among the phases of the converter occurs due to non-uniform irradiation and temperature of the cells. This causes unbalanced grid currents which is not acceptable according to the standard grid codes. A fundamental zero sequence voltage is therefore injected to balance the grid currents. But, high degree of unbalance in power generation among the phases leads to over modulation in the cells. This can happen during failure of PV modules. To avoid the over modulation, a novel zero sequence voltage is proposed in this paper. It increases the power balancing capability of the converter. The zero sequence voltage injection is implemented through a novel PWM clamping method. For obtaining the novel zero sequence voltage, a control scheme is also presented. The proposed technique is verified through simulation in MATLAB Simulink and through experiment in the lab prototype.

The full-bridge submodule (FBSM)-based modular multilevel converter (FBSM-MMC) offers promising performance due to its ability to output negative FBSM voltage. This paper studies this ability of the FBSM-MMC under zero-sequence voltage injection (ZSVI) and second-order harmonic current injection (SHCI). The focus of the research is to redistribute the FBSM powers by injecting an additional power degree of freedom, resulting in a smaller FBSM capacitor voltage ripple, while keeping the maximum AC output voltage for a given fundamental frequency component of the arm voltage reference. Accordingly, a control strategy was developed, based on non-sinusoidal ZSVI, and SHCI is proposed for further improving the performance of the FBSM-MMC. The proposed non-sinusoidal ZSVI contains a higher sinusoidal third-order harmonic component than that of pure sinusoidal third-order voltage injection (THVI) when operating under the same maximum AC output voltage. By implementing this solution, a smaller amplitude of the injected second-order harmonic current can be achieved, producing a lower power loss in the FBSM-MMC. Considering the proposed solution, the relationship of the arm powers and FBSM capacitor voltages are also discussed. Finally, the simulation results and experimental results are presented to verify the effectiveness of the theoretical analysis of the proposed method.

DC voltage balance based on zero sequence voltage is commonly used for star-connected cascaded H-Bridge (SCHB) STATCOM to compensate negative sequence current. However, zero sequence voltage injection brings about side-effect of increasing STATCOM output voltage and thus the Negative sequence Current Compensation Range (NCCR) is significantly limited to avoid overmodulation. To extend the NCCR, improving the dc voltage utilization by injecting third harmonic component is a typical method. Compared with third harmonic injection (THI), square wave features lower peak-to-average ratio. Unfortunately, the capability of square wave injection (SWI) for the NCCR extension has not been well explored. In this article, to further extend NCCR, not only the SWI is employed for SCHB STATCOM, but also it is compared with THI in term of NCCR by establishing the relationship between the maximum STATCOM voltage and negative sequence current. The comparison results reveal that the THI and SWI both have their own strengths and weaknesses in NCCR, which highly depends on the amplitudes and phases of positive and negative sequence currents. Furthermore, the criteria associated with the amplitudes and phases of the positive and negative sequence currents are derived to determine the harmonic injection method with larger NCCR by using symbolic-graphic combination method and MATLAB tools. As a result, a new harmonic injection method is proposed by selecting the THI or SWI with larger NCCR flexibly according to the amplitudes and phases of positive and negative sequence currents. Finally, the proposed method is verified by experimental results on a 400 V/7.5 kVar SCHB STATCOM prototype.

A full order continuous time generalized averaging approach for modelling of modular dual active bridge (MDAB) converter in a three stage type D modular solid state transformer (SST) is presented. Modelling of the high frequency AC (HFAC) link inductor current of MDAB can not be achieved by conventional averaging method that relies on small ripple criterion. Generalized averaging modelling method has been employed to arrive at a full order model for the MDAB. A linearised small signal model is also derived based on this and integrated with the grid connected cascaded multilevel front end converter(CMFEC).

Solid state transformer (SST), as one of the most important technologies for energy internet application, will play a crucial role in the future especially with the the development of semiconductor technology. In this paper, a simplified 5.96 MVA three-phase SST system based on 15kV silicon carbide (SIC) power semiconductor devices is shown in order to solve some disadvantages of the three-phase cascaded modular SST. The simplified topology has a great practical prospect, such as urban rail transit power supply of most cities in china. The two stages of SIC-SST, front-end rectifier and DC/DC converter are both designed in closed loop, and then a novel control strategy under unbalanced grid voltages by suppressing the negative-sequence currents at the grid side of SST is presented. Simulation results in PSIM software have verified the effectiveness of the proposed control strategy.

The parallel three-phase grid-connected converters (GCCs) with common dc and ac buses can increase the system power level effectively. However, zero sequence circulating current (ZSCC) will occur inevitably. In this paper, the mechanisms and characteristics of ZSCC in two parallel three-phase GCCs are first investigated based on three typical cases. From the analysis, it was found that not all ZSCC can be suppressed. Generally speaking, ZSCC caused by inconsistent modulation voltages between modules cannot be effectively handled. And ZSCC caused by different injected zero sequence voltages (ZSVs) or asynchronous carriers can be suppressed. Based on the theoretical analysis, identical ZSV injection and carrier synchronization methods without communication are, thus, proposed to suppress ZSCC at the source, which are easily implemented without adding any hardware. Finally, the theoretical analysis and the effectiveness of the proposed methods on ZSCC suppression are well-verified by experiments.

The solid-state transformer (SST) has the ability to operate with only two input phases, which can be called single-phase open-circuit (SPO) operation. With this ability, the SST can maintain operation under permanent single-phase-to-ground faults, where the fault phase must be isolated, providing a better power supply sustainability than that of the conventional low-frequency transformer. In the absence of research on the SPO operation of an SST, this paper presents a study of it. The influence of SPO operation on the grid and the SST itself is analyzed. Under the SPO state, the SST will inject the negative-sequence current to the grid; meanwhile, the maximum load power will decline; thus, the optimized power factor under the SPO state is unity. The maximum power of △-SST is higher than that of the Y-SST under the SPO state owing to the △ connection. A control strategy for the SST medium-voltage cascaded H-bridge stage is proposed. SPO current control can be achieved by controlling the positive-sequence current. A proper negative-sequence voltage can be injected to synchronize the cluster voltages to obtain a lower current total harmonic distortion and smaller dc voltage ripple. In the △-SST, a proper zero-sequence current can be injected to fully use the power rating of the double-cluster branch.

In a modular multilevel converter (MMC) system, the sub‐module capacitors account for a large proportion of the cost, volume, and weight. This paper proposed a method to reduce the total capacitance of MMC based on the combination of boosting the modulation index (m) and second‐harmonic circulating current injection (SCCI). A small amount of full‐bridge sub‐modules was added to conventional half‐bridge sub‐modules (HBSM) based MMC to form the hybrid MMC. The third‐harmonic voltage injection technology was used to increase the m of hybrid MMC without the common‐mode voltage injected on the ac‐side. An optimized SCCI method determined by m was introduced, which limited the root mean square (RMS) of arm current. An improved modulation approach is used to eliminate the coupling effect of third‐harmonic voltage injection and SCCI in boosting m, ensuring that the m increases to 1.15 with the optimized SCCI. Compared with conventional HBSM‐MMC, the proposed method reduced the total capacitance by approximately half when m = 1.15. A comprehensive comparison of different capacitance reduction methods was presented to demonstrate the cost and effect. Simulation and experiment verified the proposed method.

This thesis is focused on the modular multilevel converter (MMC) for High-Voltage DC (HVDC) systems. It is an attempt to address the issues associated with the modelling, simulation, control, efficiency, and fault-handling capability of the MMC. Thus, to address the modelling of the MMC, a new and more accurate steady-state harmonic model is proposed. The proposed harmonic model is capable of predicting the amplitude of the harmonic components of the MMC arm voltages, submodule capacitor voltages, and arm currents. Further, based on the proposed harmonic model, a capacitor sizing method is proposed to determine the capacitance of the submodule capacitor for a desired level of voltage variation, without a need for numerical algorithms or graphs used by the existing methods. In addition, the proposed capacitor sizing method can accurately determine the required capacitance even if circulating currents are injected to mitigate dc voltage fluctuations. The thesis also proposes a simple equivalent-circuit-based simulation model for MMC-based HVDC systems, which assumes ideal submodule switches to speed up the simulation, but is nonetheless capable of capturing the transients as well as harmonic components of the voltages and currents. Further, the thesis proposes a simple compensation strategy that calculates the magnitude of the second harmonic component of an arm voltage, and uses the calculated value as a feedforward signal to cancel the circulating current of the corresponding MMC leg. The proposed feedforward compensation strategy, if combined with a closed-loop circulating current suppression strategy, greatly mitigates the possibility of control saturation and, also, results in better damped closed-loop dynamics. Finally, the thesis proposes two new MMC topologies for enhanced efficiency and dc-side fault handling capability. In the first proposed topology, that is the lattice modular multilevel converter (LMMC), the entire MMC arm is modified to accommodate networks that allow shortcuts between the arm capacitors, thus, reducing conduction power losses of the converter. In the second topology proposed, however, only the submodule is modified. In the proposed submodule topology, referred to as lattice submodule (LSM), the conduction power losses are decreased, as it is the case for the LMMC, with the difference that the voltage stress in the switches are also reduced. Keywords: Control, lattice modular multilevel converter, lattice submodule, modelling, modular multilevel converter, simulation model.