Advanced CMOS process for floating gate field-effect transistors in bioelectronic applications

We have studied direct RF undersampling reception to reduce the size and power consumption. We already developed a series/shunt switching type sample and hold (S/H) integrated circuit (IC) by using 90 nm complementary metal oxide semiconductor (CMOS) process for Ka-band (19.4 - 20.2 GHz) very small aperture terminal (VSAT) application. This IC performed signal-to-noise ratio (SNR) of higher than 27.3 dB. For the higher frequency operation and the reception of multi-level modulated signal, the SNR improvement will be required. In this paper, a 28 GHz-band S/H IC with higher SNR has been developed. In order to improve SNR at higher RF frequency, 65 nm CMOS process is introduced to enhance the switching speed of sampling, the size of hold capacitor is optimized and the two-stage output buffer amplifier is employed. The fabricated S/H IC performs the SNR of higher than 41.2 dB and the error vector magnitude (EVM) of 4.4% (32 Mbaud 64 quadrature amplitude modulation (QAM)) in 28 GHz-band.

Resistive humidity microsensor with circuit manufactured by the CMOS process

DNA origami, in which a long single strand of DNA is folded into a shape using shorter `staple Strands', promises low-cost ways to create nanoscale shapes and can even display patterns of binding sites of 6-nm-resolution, in principle allowing complex arrangements of carbon nanotubes, silicon nanowires, or quantum dots [1]. However, adsorption of origami appears better results on mica substrate, which cannot compatible with the complementary metal oxide semiconductor (CMOS) process. Here we describe a method to improve the adsorption of origami on silicon substrate, by quantitative control of the adsorption conditions, which will hopefully make contributions for churning out nanoscale shapes with CMOS process in the future.

This paper presents the fabrication and characterization of energy harvesting thermoelectric micro generators using the commercial complementary metal oxide semiconductor (CMOS) process. The micro generator consists of 33 thermocouples in series. Thermocouple materials are p-type and n-type polysilicon since they have a large Seebeck coefficient difference. The output power of the micro generator depends on the temperature difference in the hot and cold parts of the thermocouples. In order to increase this temperature difference, the hot part of the thermocouples is suspended to reduce heat-sinking. The micro generator needs a post-CMOS process to release the suspended structures of hot part, which the post-process includes an anisotropic dry etching to etch the sacrificial oxide layer and an isotropic dry etching to remove the silicon substrate. Experiments show that the output power of the micro generator is 9.4 μW at a temperature difference of 15 K.

Multistandard RF chips have been highly demanded for multipurpose wireless applications. However, in RF circuits, a low-noise amplifier (LNA) plays an important role in determining the receiver's performance. In this paper, we present a scalable wideband LNA based on complementary metal oxide semiconductor (CMOS) inverters, employing two bandwidth expansion techniques to achieve a large bandwidth without using inductors. Fabricated by the 40 nm CMOS process, the LNA attains 0.1–8.0 GHz of flat bandwidth with S21=17.5 dB and S11≤-10 dB. The minimum NF measured is 5.1 dB and the power consumption is 14.3 mW at 1.3 V. The LNA core circuit is as small as 0.001 mm2 since no large passive device is used. A study of LNA scalability has been conducted by comparing the performances of circuits with the same topology fabricated by the 65, 90, and 180 nm CMOS processes.

A complementary metal oxide semiconductor (CMOS) voltage‐controlled oscillator (VCO) using a tail current source modulated with the output frequency is presented to achieve low phase noise with low power consumption at the K‐band. Differentially modulated current sources, which reduce flicker noise by the feedback of the VCO outputs, contribute to an overall reduction in the phase noise of the VCO using the electromagnetic‐based fully symmetrical design. The proposed LC VCO with a 3‐bit switched capacitor bank for a wide tuning range was fabricated on the size of 0.4 × 0.57 mm2 using a 65‐nm CMOS process. The measurement results of the proposed VCO showed a frequency tuning range from 22.57 to 25.3 GHz, and a phase noise of −108.48 dBc/Hz at a 1‐MHz offset frequency with a power consumption of 8.27 mW at a supply voltage of 1.2 V. The calculated figure of merit (FoM) and FoM with the tuning range were −186.48 and −187.67 dBc/Hz, respectively.

Metal gate technology for nanoscale transistors—material selection and process integration issues

: The goal of this research was to develop an embedded magnetic memory technology to be integrated into Complementary Metal Oxide Semiconductor (CMOS) integrated circuit fabrication process to provide radiation-hard, logic elements and small random-access memories. The goal is not to provide large scale, bulk memory, but latches and flip flops that serve as state and data registers for sequential logic, and configuration registers for configurable logic. The benefits to spacecraft systems include the ability to power-down a subsystem while retaining system state, thus saving energy until the subsystem is required. The subsystem can then be powered-up and begin operating in milliseconds. The technology is based on a unique, PacMan-shaped magnetic tunneling junction (MTJ) cell developed at the University of Idaho. The focus of this research is to refine the PacMan cell to make it practical for integration into CMOS circuits, to develop CMOS circuits that employ the magnetic cells, and to integrate the cells onto a CMOS process. The process produced two circuit designs based on magnetic memory elements: a magnetic latch, and a magnetic shadow memory to serve as a backup to volatile electronic memory.

Latch-up in CMOS (Complementary Metal-Oxide-Semiconductor) technology is a significant reliability concern in VLSI (Very Large Scale Integration) design. Latch-up is a parasitic, unintended creation of a low-impedance path between the power supply rails due to the triggering of parasitic thyristor structures inherent in CMOS processes. This phenomenon can lead to device malfunction, excessive current flow, and potential permanent damage to the integrated circuit. The impact of latch-up is profound, as it compromises the stability and functionality of electronic systems, especially in high-performance and high-reliability applications such as aerospace, medical devices, and critical infrastructure. The primary factors contributing to latch-up include high current spikes, radiation exposure, and improper circuit layout. Preventive measures are essential to mitigate these risks and ensure the robustness of CMOS circuits. Effective prevention strategies include the use of guard rings, which isolate the sensitive regions of the chip and prevent the formation of parasitic paths. Proper substrate doping and well design can also minimize latch-up susceptibility. Additionally, optimizing the layout design to minimize the proximity of p-n junctions and employing advanced CMOS processes with latch-up resistant technologies are crucial. This abstract highlights the importance of understanding and preventing latch-up in CMOS VLSI design to enhance the reliability and performance of modern integrated circuits.

A 4 x 4 pixel array with analog on-chip processing has been fabricated within a 0.35 mum complementary metal oxide semiconductor process as a prototype sensor for laser Doppler blood flow imaging. At each pixel the bandpass and frequency weighted filters necessary for processing laser Doppler blood flow signals have been designed and fabricated. Because of the space constraints of implementing an accurate omega(0.5) filter at the pixel level, this has been approximated using the "roll off" of a high-pass filter with a cutoff frequency set at 10 kHz. The sensor has been characterized using a modulated laser source. Fixed pattern noise is present that is demonstrated to be repeatable across the array and can be calibrated. Preliminary blood flow results on a finger before and after occlusion demonstrate that the sensor array provides the potential for a system that can be scaled to a larger number of pixels for blood flow imaging.

Co silicide spikes have been found in active contact salicidation in complementary metal oxide semiconductor devices during failure analysis by means of transmission electron microscopy examination. Scanning transmission electron microscopy, energy dispersive x-ray analysis and microdiffraction study revealed that these spikes are CoSi2 with an epitaxial relationship with Si of (111)CoSi2//(111)Si and [11̄0]CoSi2//[11̄0]Si. The formation of the CoSi2 spikes are suspected to be due to the presence of undesired SiOx residue between Co film and Si substrate which acts as a solid diffusion membrane to cause the Si rich phase CoSi2 to precipitate directly inside Si lattice.

The fabrication of a Blood Pressure Sensor and Intracranial Pressure monitoring using the TSMC 0.35 um complementary metal oxide semiconductor process and a post-process have been investigated. The metal layers of the CMOS process are used as the sensing electrodes and sacrificial layers, with the cavity spacing about 0.64um. Finally the etching holes in the pressure sensor are sealed with SU8 or sputter deposition Al. This sensor is composed of eight sensing cells containing four variable capacitors and four reference capacitors. The variable and reference capacitors are parallel respectively, able to increase the sensitivity of the sensor. The pressure sensor is connected to fully-differential capacitive sensing circuit that readouts the capacitor variable value. The experimental results show that the pressure sensor has a capacitance variance of 0~88fF, and the sensitivity of 2.076 fF/kPa in pressure measurement range of 0~42.38kPa.

ABSTRACTThis work focuses on the subthreshold design of ultra low‐voltage low‐power operational amplifiers. A well‐defined procedure for the systematic design of subthreshold operational amplifiers (op‐amps) is introduced. The design of a 0.5‐V two‐stage Miller‐compensated amplifier fabricated with a 0.18‐µm complementary metal–oxide–semiconductor process is presented. The op‐amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain–bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is ≈0.057 mm2. Experimental results demonstrate that well‐designed subthreshold op‐amps are a very attractive solution to implement sub‐1‐V energy‐efficient applications for modern portable electronic systems. A comparative analysis with low‐voltage, low‐power op‐amp designs available in the literature highlights that subthreshold op‐amps designed according to the proposed design procedure achieve a better trade‐off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/−0.52 least significant bit and +0.62/−0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.

In this work, the authors propose a 4F2 (F is the length of half pitch) memory cell with a vertical PNPN structure (silicon device with 4 layers doped with p-type, n-type, p-type and n-type dopants, respectively) to increase static random access memory (SRAM) integration density compared to the traditional 6T SRAM cell with an area of 90 ∼ 150F2. Thanks to the simple two-terminal configuration, the cross-point structure with proposed cell can be used in memory design, to achieve the highest density in planar complementary metal oxide semiconductor (CMOS) technology and to be implemented potentially in future three-dimensional integration. Experimental results demonstrate that the fabrication of proposed memory cell is compatible with CMOS process, little impact by process variation and reliability issues. Calibrated simulations display that the proposed cell can be programmed at nanosecond level speed with acceptable power consumption in most memory applications.