Advances in Sensing Methodology for Resistive RAM

The resistive random access memory (RRAM) device has been widely studied due to its excellent memory characteristics and great application potential in different fields. In this paper, resistive switching materials, switching mechanism, and memory characteristics of RRAM are discussed. Recent research progress of RRAM in high-density storage and nonvolatile logic application are addressed. Technological trends are also discussed.

The modern-day computing technologies are continuously undergoing a rapid changing landscape; thus, the demands of new memory types are growing that will be fast, energy efficient and durable. The limited scaling capabilities of the conventional memory technologies are pushing the limits of data-intense applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Resistive random access memory (RRAM) is one of the most suitable emerging memory technologies candidates that have demonstrated potential to replace state-of-the-art integrated electronic devices for advanced computing and digital and analog circuit applications including neuromorphic networks. RRAM has grown in prominence in the recent years due to its simple structure, long retention, high operating speed, ultra-low-power operation capabilities, ability to scale to lower dimensions without affecting the device performance and the possibility of three-dimensional integration for high-density applications. Over the past few years, research has shown RRAM as one of the most suitable candidates for designing efficient, intelligent and secure computing system in the post-CMOS era. In this manuscript, the journey and the device engineering of RRAM with a special focus on the resistive switching mechanism are detailed. This review also focuses on the RRAM based on two-dimensional (2D) materials, as 2D materials offer unique electrical, chemical, mechanical and physical properties owing to their ultrathin, flexible and multilayer structure. Finally, the applications of RRAM in the field of neuromorphic computing are presented.

This chapter introduces resistive random-access memory (RRAM), a futuristic memory technology that excels its counterparts in terms of reliability, nano-scale dimensions, energy per bit, and fast read/write times. Also, it is promising for use in neuromorphic computing and digital applications. However, the major challenge encountered during the progress of the technology is the presence of leakage current (sneak path current) while using it in crossbar arrays. Various techniques are employed to mitigate the sneak current problem. However, associating a selector with RRAM is an efficient method. To study the one selector-one RRAM (1S-1R) characteristics, the electrical model of the selector, as well as RRAM, is necessary; therefore, this chapter discusses the electrical modeling of selector device (1S), RRAM devices (1R), integration of selector models with the RRAM model (1S-1R), and formation of 1S-1R crossbar arrays. The selector device used to model this is Pt/Ta2O5/TaOx /TiO2/Pt, and the RRAM model adopted is Pt/Ta2O5/TaOx/Pt. Further, various parameters are analyzed, such as R off /R on ratio, nonlinearity, and off-current are improved in the 1S-1R cell compared to RRAM characteristics. Besides, it is perceived that 98% of the sneak path current is mitigated in the 1S-1R crossbar array compared to the 1R crossbar array.

Resistance random access memory (RRAM) based on resistive switching in metal oxides has attracted considerable attention as a promising candidate for next-generation nonvolatile memory due to its high operating speed, superior scalability, and low power consumption. However, some operating parameters of RRAM cannot meet the practical requirement, which impedes its commercialization. A lot of experimental results show that doping is an effective method of improving the performance of RRAM, while the study on the physical mechanism of doping is rare. It is generally believed that the formation and rupture of conducting filaments, caused by the migration of oxygen vacancies under electric field play a major role in resistive switching of metal oxide materials. In this work, the first principle calculation based on density functional theory is performed to study the effects of transition metal element X (X=Mn, Fe, Co, and Ni) doping on the migration barriers and formation energy of oxygen vacancy in ZnO. The calculation results show that the migration barriers of both the monovalent and divalent oxygen vacancy are reduced significantly by Ni doping. This result indicates that the movement of oxygen vacancies in Ni doped ZnO is easier than in undoped ZnO RRAM device, thus Ni doping is beneficial to the formation and rupture of oxygen vacancy conducting filaments. Furthermore, the calculation results show that the formation energy of the oxygen vacancy in ZnO system can be reduced by X doping, especially by Ni doping. The formation energy of the oxygen vacancy decreases from 0.854 for undoped ZnO to 0.307 eV for Ni doped ZnO. Based on the above calculated results, Ni doped and undoped ZnO RRAM device are prepared by using pulsed laser deposition method under an oxygen pressure of 2 Pa. The Ni doped ZnO RRAM device shows the optimized forming process, low operating voltage (0.24 V and 0.34 V for Set and Reset voltage), and long retention time (>104 s). Set and Reset voltage in Ni doped ZnO device decrease by 80% and 38% respectively compared with those in undoped ZnO device. It is known that the density of oxygen vacancies in the device is dependent on the oxygen pressure during preparation. The Ni doped ZnO RRAM device under a higher oxygen pressure (5 Pa) is also prepared. The Ni doped ZnO RRAM device prepared under 5 Pa oxygen pressure shows a little higher Set and Reset voltage than the device prepared under 2 Pa oxygen pressure, while the operating voltages are still lower than those of undoped ZnO RRAM. Thus, the doping effect in the ZnO system is affected by the density of oxygen vacancies in the device. Our work provides a guidance for optimizing the performance of the metal oxide based RRAM device through element doping.

We investigated the reliability of resistive random access memory (ReRAM) under two different types of incremental step pulse programming (ISPP) along with the yield enhancement by the customized programming pulses based on the susceptibility of memory cells. Adaptive step-size control of ISPP enabled by an analog-to-digital converter (ADC) based sense amplifier significantly reduces the cycling disturbance by 54% because of the decreased number of effective write accesses. The programming yield of ReRAM was further improved with a proposed write scheme. The defective ReRAM cells are classified as soft fail cells and hard fail cells by the ADC-based sense amplifier, and soft fail cells are rescued by using a modified programming pulse. Measurements verified that the programming yield drop of 3% is completely recovered by the program pulse shaping.

Design of RRAM with high storage capacity and high reliability for IoT applications

The traditional von Neumann architecture limits the increase in computing efficiency and results in massive power consumption in modern computers due to the separation of storage and processing units. The novel neuromorphic computation system, an in-memory computing architecture with low power consumption, is aimed to break the bottleneck and meet the needs of the next generation of artificial intelligence (AI) systems. Thus, it is urgent to find a memory technology to implement the neuromorphic computing nanosystem. Nowadays, the silicon-based flash memory dominates non-volatile memory market, however, it is facing challenging issues to achieve the requirements of future data storage device development due to the drawbacks, such as scaling issue, relatively slow operation speed, and high voltage for program/erase operations. The emerging resistive random-access memory (RRAM) has prompted extensive research as its simple two-terminal structure, including top electrode (TE) layer, bottom electrode (BE) layer, and an intermediate resistive switching (RS) layer. It can utilize a temporary and reversible dielectric breakdown to cause the RS phenomenon between the high resistance state (HRS) and the low resistance state (LRS). RRAM is expected to outperform conventional memory device with the advantages, notably its low-voltage operation, short programming time, great cyclic stability, and good scalability. Among the materials for RS layer, indium gallium zinc oxide (IGZO) has shown attractive prospects in abundance and high atomic diffusion property of oxygen atoms, transparency. Additionally, its electrical properties can be easily modulated by controlling the stoichiometric ratio of indium and gallium as well as oxygen potential in the sputter gas. Moreover, since the IGZO can be applied to both the thin-film transistor (TFT) channel and RS layer, it has a great potential for fully integrated transparent electronics application.In this work, we proposed amorphous transparent IGZO-based RRAMs and investigated switching behaviors of the memory cells prepared with different top electrodes. First, ITO was choosing to serve as both TE and BE to achieve high transmittance. A multi-target magnetron sputtering system was employed to deposit all three layers (TE, RS, BE layers) on glass substrate. I-V characteristics were evaluated by a semiconductor parameter analyzer, and the bipolar RS feature of our RRAM devices was demonstrated by typical butterfly curves. The optical transmission analysis was carried out via a UV-Vis spectrometer and the average transmittance was around 80% out of entire devices in the visible-light wavelength range, implying high transparency. We adjusted the oxygen partial pressure during the sputtering of IGZO to optimize the property because the oxygen vacancy concentration governs the RS performance. Electrode selection is crucial and can impact the performance of the whole device. Thus, Cu TE was chosen for our second type of device because the diffusion of Cu ions can be beneficial for the formation of the conductive filament (CF). A ~5 nm SiO2 barrier layer was employed between TE and RS layers to confine the diffusion of Cu into the RS layer. At the same time, this SiO2 inserting layer can provide an additional interfacial series resistance in the device to lower the off current, consequently, improve the on/off ratio and whole performance. Finally, an oxygen affinity metal Ti was selected as the TE for our third type of device because the concentration of the oxygen atoms can be shifted towards the Ti electrode, which provides an oxygengettering activity near the Ti metal. This process may in turn lead to the formation of a sub-stoichiometric region in the neighboring oxide that is believed to be the origin of better performance.In conclusion, the transparent amorphous IGZO-based RRAMs were established. To tune the property of RS layer, the sputtering conditions of RS were varied. To investigate the influence of TE selections on switching performance of RRAMs, we integrated a set of TE materials, and a barrier layer on IGZO-based RRAM and compared the switch characteristics. Our encouraging results clearly demonstrate that IGZO is a promising material in RRAM applications and breaking the bottleneck of current memory technologies.

Resistive random access memory (RRAM) is one of the universal memory candidates for computer systems. Although RRAM promises many attractive advantages (e.g., huge data storage, smaller form-factor, lower power consumption, non-volatility, etc.), there are many open issues that still need to be solved, especially those related to its quality and reliability. For instance, open defects may cause RRAM cell to enter an undefined state (i.e., somewhere between logic 0 and 1), making it hard to detect during manufacturing test. As a consequence, this may lead to test escapes (quality issue) and field failures (reliability issue). This paper shows - based on defect and circuit simulation - how testing RRAM is different from testing conventional random access memories and how march test cannot guarantee higher defect coverage. The paper then motivates the need of development of special Design-for-Testability (DfT). A concept of a new DfT is then proposed. The concept is further exploited and mapped into two different DfT circuitries: (i) Short Write Time and (ii) Low Write Voltage. Both DfT schemes are implemented and simulated; the simulation results show that defects causing the RRAM cell to enter an undefined state are easily detected.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of random-access memory which is not desired and is considered as a challenge for memory cell.

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic randomaccess memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive randomaccess memory (RRAM), magnetoresistive randomaccess memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of randomaccess memory which is not desired and is considered as a challenge for memory cell.

In this paper, the switching layer thickness and temperature impacts on resistance switching polarity of tantalum oxide (TaO x ) based resistive random access memory (RRAM) have been investigated. Our results show that at room temperature unipolar behavior was activated in thick TaO x but failed in thin TaO x , while in 280 °C condition thin TaO x layer RRAM can also show stable unipolar characteristics. For thick TaO x device, the unipolar behavior is attributed to more heat accumulation in thicker switching layer. In 280 °C condition, stable unipolar characteristic of thin TaO x device is due to extra ambient heat offered. In addition, thin TaO x RRAM with Si0 2 buffer layer is also fabricated to investigate the heat accumulation impact on operation polarity of RRAM devices. These results are helpful in obtaining the insight on understanding the switching mechanism of TaO x RRAM and improve the RRAM device performance and reliability capability.

Recent advances in the performance of resistive random access memory (RRAM) have engendered significant interest for system-on-chip (SoC) applications in Si-based CMOS technologies1, including various wireless sensor networks (WSNs) and medical health care devices. For most applications, the realization of energy-efficient sensor nodes with a high lifetime provides the prospect of completely autonomous systems. Recent hardware-based approaches to obtain energy-efficient sensor nodes focus on the integration of RRAM in a microcontroller unit (MCU) 2.Given the wide range of possible transition metal oxides, HfO2-based RRAM provides an ideal CMOS back-end-of-line (BEOL) compatibility with sufficient performance parameters and thus considerable progress has been made in integrating RRAM devices as well as in understanding the physical/chemical properties of the resistive switching behavior3,4. It still remains difficult in HfO2-based RRAM to further reduce energy dissipation and in addition to increase reliability for autonomous sensor nodes. To address this issue, RRAM integration aspects are accompanied by fundamental materials research studies.First, non-destructive and in-operando Hard X-ray Photoelectron Spectroscopy (HAXPES) 5,6 (Fig. 1(a)) was performed to correlate the RS characteristics for increased current compliance (CC) with materials modifications at the HfO2/Ti interface. HAXPES data indicate that the RS behvior does not only affect the Ti 2p, Hf 4f and O 1s photoemission lines but also C 1s (Fig. 1(b)). After survey spectra normalization to the Hf 4d peak intensity, the C 1s peak intensity increases with the increase of the electrical stress applied to the sample. After electroforming, the C 1s to Hf 4d intensity ratio IC/IHf increases from 0.4 (as-deposited-state) to 0.6 (ON-state 30 mA CC). This result indicates that carbon present in the HfO2film cannot be neglected and its role on the RS behavior of RRAM cells should be investigated in more detail. Obtained results will be presented.The fundamental materials research insights were then transferred to integrated 4 kbit RRAM test modules with the associated control circuitry 5 (Fig. 1(c)). Due to the statistic nature of the electroforming process as well as due to process-induced variation, the inter-cell variability of memory elements in a memory array after electroforming and during RS must be studied. To address the point above, Fig. 1 (d)-(e) shows the current distribution in the initial state (d) and after DC forming (e) for one 64 × 64 bit (4 kbit) memory device array. We note that the initial state shows inter-cell variability which affects the DC forming process. Statistical analysis reveals that some memory elements were conductive with a current of >1×10−5A and could thus not be formed. The presentation will summarize further results on inter-cell and intra-cell variability for a 4 kbit memory array.This work is financially supported by the German research foundation DFG under contract SCHR1123/7-1.[1] J. Suhonen et al. Low-Power Wireless Sensor Networks, Springer, (2012).[2] Y. Zhang, Future Wireless Networks and Information Systems, Springer, (2012).[3] S.-S. Sheu et al., Proc. ISSCC, pp. 200–202, (2011).[4] Tz-Yi Liu et al., Proc. ISSCC, pp. 210–212, (2013).[5]M. Sowinska et al., Appl. Phys. Lett. 100, 233509 (2012).[6] T. Bertaud et al., Appl. Phys. Lett. 101, (2012).[7] D. Walczyk et al., ISCDG, pp. 143-146, (2012).Figure 1: (a) RRAM device mounted on a PCB inside the HAXPES vacuum chamber 5,6. (b) HAXPES survey spectra for different resistive states: as-deposited and three ON-states (CC = 6, 20 and 30 mA). C 1s spectra of the as-deposited- and ON-state (30 mA). (c) Image of the 4 kbit memory array with control circuits 7. Current distribution in the initial state (d) and after DC forming (e) for a 64 × 64 bit (4 kbit) memory device array.

Resistive random access memories (RRAM), based on the formation and rupture of conductive nanoscale filaments, have attracted increased attention for application in neuromorphic and in-memory computing. However, this technology is, in part, limited by its variability, which originates from the stochastic formation and extreme heating of its nanoscale filaments. In this study, we used scanning thermal microscopy (SThM) to assess the effect of filament-induced heat spreading on the surface of metal oxide RRAMs with different device designs. We evaluate the variability of TiO2 RRAM devices with area sizes of 2 × 2 and 5 × 5 μm2. Electrical characterization shows that the variability indicated by the standard deviation of the forming voltage is ∼2 times larger for 5 × 5 μm2 devices than for the 2 × 2 μm2 ones. Further knowledge on the reason for this variability is gained through the SThM thermal maps. These maps show that for 2 × 2 μm2 devices the formation of one filament, i.e., hot spot at the device surface, happens reliably at the same location, while the filament location varies for the 5 × 5 μm2 devices. The thermal information, combined with the electrical, interfacial, and geometric characteristics of the device, provides additional insights into the operation and variability of RRAMs. This work suggests thermal engineering and characterization routes to optimize the efficiency and reliability of these devices.

The dependency of the RRAM device electrical parameters such as set voltage, reset current and resistance on the RRAM cell dimensional scalability is investigated with Monte Carlo simulation to optimize the power consumption of bipolar RRAM. It is found in the simulation that the switching process in bipolar RRAM is related to the cell dimension in the sub-nm region in terms of its horizontal length. The suppressing effect of existing conducting filament is also discussed. With optimal cell size sufficient initial resistance and a low forming voltage will be achieved, accelerating the feasibility of the high-density low-power RRAM.

Resistive random access memory (ReRAM) is a novel form of non-volatile memory expected to replace FLASH memory in the near future. As a further step toward use of ReRAM in computer architectures, we have developed a CMOS/ReRAM hybrid process, integrating ReRAM into a CMOS process flow. In this study, we investigate yield, reliability, endurance, threshold voltages (forming, set and reset voltages) of ReRAM devices implemented in the back end of the line (BEOL). The focus of this study is on single ReRAM devices operated with an external transistor (1T1R configuration). Yield and endurance of these 1T1R configured devices show a strong dependence on device position on the wafer, the device size, and the current compliance used during the initial forming and subsequent set sweeps. Elevated temperatures resulted in a shift of the optimum operation conditions and could be used to improve device performance. Variance in performance of the ReRAM devices was directly correlated with manufacturing issues and material properties to gain maximum information for future improvements