Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight

H.264/AVC is the commercial standard currently most in use for video and is based on single view (mono view). Recently, the video community has also standardized an H.264/AVC extension for supporting 3D video sensation which is referred to as Multiview Video Coding (MVC). Like H.264/AVC, MVC includes temporal and spatial prediction but also includes inter-view prediction as well as disparity estimation. Until now, in H.264/AVC the inter prediction techniques have been the most time-consuming tasks and, thus, in MVC with its new interview predictions the encoding time is even higher. This paper proposes a GPU-based algorithm for both temporal and interview prediction. The algorithm proposed is able to perform this complex prediction task by means of an efficient distribution of all the computations over the GPU and also tries to mitigate the sequential dependencies. The approach can achieve a remarkable time reduction of up to 98% with only a negligible loss in coding efficiency. Moreover, this paper shows that the proposed GPU-based algorithm is more energy efficient and thus, requires less energy than the sequential reference.

Multi-view video coding (MVC) is an ongoing standard in which variable size disparity estimation (DE) and motion estimation (ME) are both employed to select the best coding mode for each macroblock (MB). This technique achieves the highest possible coding efficiency, but it results in extremely large encoding time which obstructs it from practical use. In this paper, a fast DE and ME algorithm based on motion homogeneity is proposed to reduce MVC computational complexity. The basic idea of the method is to utilize the spatial property of motion field in prediction where DE and variable size ME are needed, and only in these regions DE and variable size ME are enabled. The motion field is generated by the corresponding motion vectors (MVs) in spatial window. Simulation results show that the proposed algorithm can save 63% average computational complexity, with negligible loss of coding efficiency.

Multiview video coding (MVC) systems have attracted much attention because of their applications in free view point television (FTV), three-dimensional television (3DTV), surveillance systems, etc. Compared with the traditional 2D media, multiview videos usually involve large data size. It is essential to develop high performance MVC systems with low computational complexity. This thesis aims to develop an efficient multiview video codec based on the Audio Video Coding Standard of China (AVS) and investigate its application to image-based rendering (IBR).
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\nFirstly, a new fast motion estimation (ME) algorithm based on the simplified unsymmetrical hexagonal method (UMHexagonS) used in the AVS standard is developed. Different from the conventional method, the proposed approach uses an extended searching area and a square-based search to reduce computation complexity considerably. To obtain real-time implementation, we proposed a macroblock-based parallel structure which utilizes multi-core processing. Such approach can improve the encoding frame rate by approximately 4 times compared to traditional implementations. The proposed method has been tested on an Intel Core i7 3960x six cores 3.3GHz CPU. The real-time encoding speed reaches 25 frames per second (fps) for a 1280×720 high-definition video.
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\nSecondly, a multiview video coding algorithm based on AVS which encode three views as a group is developed. By taking advantages of the reduced inter-view dependency among adjacent views, the proposed algorithm can simplify the selective transmission and the decoding of multiview videos. Moreover, a new disparity estimation (DE) algorithm based on an unsymmetrical search window is proposed to further reduce the computational complexity. The developed encoder can achieve real-time encoding for 640×480 3-view videos at more than 26fps on a computer equipped with an Intel Core i7 3960x six cores 3.3GHz CPU.
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\nFinally, an image-based rendering and object-based compression system based on the Kinect depth camera and algorithm are developed for indoor applications. The proposed system uses the depth information obtained by the Kinect depth camera together with the texture information to perform IBR. Experimental results illustrate that good performance and usefulness can be achieved by the proposed approach.

Multiview video coding (MVC) is an ongoing standard. In the working draft, motion estimation and disparity estimation are both employed in the encoding procedure. It achieves the highest possible coding efficiency, but results in extremely large encoding time, which obstructs it from practical applications. We propose a macroblock (MB) level adaptive search range algorithm utilizing inter-view correlation for motion estimation in MVC to reduce the complexity of the coder. For multi-view sequences, the motion vectors of the corresponding MBs in previously coded view are first extracted to analyze motion homogeneity. On the basis of motion homogeneity, MBs are classified into three types (MB in the region with homogeneous motion, with medium homogeneous motion, or with complex motion), and search range is adaptively determined for each type MB. Experimental results show that our algorithm can save 75% average computational complexity of motion estimation, with negligible loss of coding efficiency.

Early SKIP mode decision for MVC using inter-view correlation

: This report describes techniques for very large scale integration (VLSI) implementation of arithmetic algorithms. The report describes an algorithm for performing area-time efficient division, on-line techniques for performing bit-serial calculations, and iterative algorithms for performing square root. Keywords include: Very large scale integration (VLSI); and Floating point chip design.

In this paper, a new rate---distortion (R---D) optimized error-resilient scheme is proposed to improve error resilience for multi-view video transmission over lossy networks. Based on the study on the characteristics of multi-view video coding and the propagating behavior of channel errors, a recursive model to estimate the end-to-end distortion is first developed, in which the channel-induced distortion takes into consideration both motion and disparity compensation prediction. Then, based on the estimated distortion and the derived total bit rate, R---D optimized motion and disparity estimation are employed to find the reliable motion vector and disparity vector to achieve the optimum trade-off between prediction efficiency and error robustness. Finally, R---D optimization is applied again to perform coding mode decision, which explicitly considers intra, inter and inter-view prediction modes. Extensive experimental results demonstrate significant performance gains can be achieved for multi-view video communications against transmission errors.

The challenge to H.265/HEVC multiview video coding (MVC) is its extremely high computational complexity. This paper presents the development and implementation of a scalable massively parallel fast search algorithm to significantly reduce the computational cost of motion and disparity estimation over the current best available GPU full block matching and sub optimal CPU fast search algorithms by a factor up to 2.4 and 8.4, respectively.

In single viewpoint video coding, there are many fast block matching motion estimation algorithms proposed, such as three-step search, four-step search, diamond search as well as hexagon-based search and so on. However, experimental analysis show that these algorithms are not suitable for using directly in Multiview View Coding (MVC). Since the increased search range, the larger format of multiview video as well as the correlations between inter-view frames are not considered by these algorithms, they may easy led the block matching search into local minimum, the Rate-Distortion (R-D) performance will degrade dramatically. In this paper, we propose a novel multiple hexagon search algorithm to address this problem. Firstly, according to the original initial search point, four sub-search windows are constructed. Then, the hexagon based search algorithm will be performed respectively in the four sub-search windows. The final result is the best search point with the minimum R-D cost among the best points in the four sub-search windows. In order to trade off the computational complexity and R-D performance, two adaptive early termination strategies are proposed. The experimental results show that the proposed algorithm yields a quite promising coding performance in terms of R-D performance and computational complexity. Especially, the proposed algorithm can work well in multiview video sequences with various motion and disparity activities.

The use of variable block-size motion estimation (ME), disparity estimation (DE), and multiple reference frames selection aims to improve the coding efficiency of multiview video coding (MVC), however, this is at the cost of high computational complexity of these advanced coding techniques, which are not suitable for real-time video broadcasting applications. In this paper, we propose an efficient ME and DE algorithm for reducing the computational complexity of MVC. Firstly, according to the characteristics of the coded block pattern and rate distortion (RD) cost, an early DIRECT mode decision algorithm is proposed. Then, based on the characteristics of the initial search point in the ME/DE process and the observation that the best point is center-biased, an early ME/DE termination strategy is proposed. If the ME/DE early termination is not satisfied, the ME/DE search window will be reduced by applying the optimal theory. At last, two block matching search strategies are proposed to predict the best point for the ME/DE. Experimental results show that the proposed algorithm can achieve 50.05% to 77.61%, 64.83% on average encoding time saving. Meanwhile, the RD performance degradation is negligible. Especially, the proposed algorithm can be applied to not only the odd views but also the even views.

Although sorting networks have extensively been reported in literature (Batcher, 1962), there are a few references that cover a detailed explanation about their VLSI (Very Large Scale of Integration) realization in CMOS (Complementary Metal-Oxide-Semiconductor) technology (Turan et al., 2003). From an algorithmic point of view, a sorting network is defined as a sequence of compare and interchange operations depending only on the number of elements to be sorted. From a hardware perspective, sorting networks can be visualized as combinatorial circuits where a set of denoted compare-swap (CS) circuits can be connected in accordance to a specific network topology (Knuth, 1997). In this chapter, the design of sorting networks in CMOS technology with applicability to VLSI design is approached at block, transistor, and layout levels. Special attention has been placed to show the hierarchical structure observed in sorting schemes where the so called CS circuit constitutes the fundamental standard cell. The CS circuit is characterized through SPICE simulation making a particular emphasis in the silicon area and delay time parameters. In order to illustrate the inclusion of sorting networks into specific applications, like signal processing and nonlinear function evaluation, two already reported examples of integrated circuit designs are provided (Agustin et al., 2011; Jimenez et al., 2011).

Process quality and delivery time have received increasing attention in the highly competitive electronics industry. Many studies have proposed process capability indices (PCIs) to assess process effectiveness. However, methods to assess the performance in terms of processing and delivery times of products have seldom been discussed. The conventional PCIs can no longer assess the processing time (PT) and delivery time (DT) performance objectively or identify the relationship between PCIs and the non-conformance rate of PT or the conformance rate of DT. Lacking an effective performance index or an objective testing procedure to assess process/product performance will lead to inefficiency or a high manufacturing management overhead cost. Therefore, this study offers effective performance indices (i.e., PCIs) to assess the PT and DT performance for very large scale integration (VLSI). The uniformly minimum variance unbiased (UMVU) estimators of the proposed PCIs are derived under the assumption of a normal process distribution. The PCI estimators are then employed to construct a one-to-one relationship between the PCIs and the conformance rate of DT or non-conformance rate of PT, respectively. Finally, hypothesis testing procedures for the proposed PCIs are also developed. The testing procedure can be used to determine whether DT or PT can satisfy a customer’s requirements.

The construction of computer systems containing integrated circuit logic components with very large scale integration (VLSI), that is, many thousands of gates, is inevitable. Such levels of integration have already been achieved in memory components. There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.

Very large scale Integration (VLSI) was used to create hardware which initiates by the explanation of algorithm as well as employs computer program. In digital systems, multiplier and adder are the fundamental components in design of integrated circuit applications. High speed devices play an essential role in VLSI applications. Adder enhancement is used in miscellaneous application in new VLSI system like multiplier design, ALU and etc. An efficient adder circuit design is used to optimize various metrics. But, design complexity was not reduced by existing VLSI design. To handle such limitations, Deep Fully Connectedness Convolutional Broken Stick Regressive Brent-Kung Adder Enhancement (DFCCBSRBKAE) Technique is introduced in VLSI circuits. Input layer, two hidden layers as well as output layer comprises four layer of DFCCBSRBKAE Technique. The carry inputs are transferred to input layer. Input data is transferred to hidden layer 1. Broken-stick regression analysis is performed for pre-processing data. Next, pre-processed data is transferred to hidden layer 2. Carry generation and post-processing is carried out in hidden layer 2 and the output results are covered by the convolution. At last, outcomes were attained within output layer. This in turn helps to perform an efficient adder enhancement of digital multiplier with minimal power and time consumption. The performance of DFCCBSRBKAE Technique is determined by power and time consumption. DFCCBSRBKAE Technique reduces the area, speed, and delay and power consumption of adder enhancement compared with conventional methods.

In this paper, a new version of very large scale integration (VLSI) layouts compaction problem is considered. Bar visibility graph (BVG) is a simple geometric model for VLSI chip design and layout problems. In all previous works, vertical bars or other chip components in the plane model gates, as well as edges, are modeled by horizontal visibilities between bars. In this study, for a given set of vertical bars, the edges can be modeled with orthogonal paths known as staircases. Therefore, we consider a new version of bar visibility graphs (BsVG). We then present an algorithm to solve the s-visibility problem of vertical segments, which can be implemented on a VLSI chip. Our algorithm determines all the pairs of segments that are s-visible from each other.