Algorithms and Data Structures for Parametric Analysis of Real-Time Systems

Real-time software is becoming more prevalent in avionics systems such as unmanned aerial vehicles and spacecrafts. More often, these systems operate with limited human interaction or an increased latency in human response. Therefore, these systems require autonomous fault detection and a repair mechanism to respond to off nominal conditions that could arise. In order to prevent a hazard, these systems require assurance that they will operate in a safe manner while successfully completing a mission. Assurance, as a software engineering activity involves the reduction of risk, and inversely, an increase in confidence in a software system. In the context of fault management, this becomes a question of increasing confidence that a software system can detect and respond to the offnominal conditions occur. This activity is not always straight forward as off-nominal conditions in complex real-time systems do not always manifest as singular events, but rather as a combination of symptoms. Furthermore, for fault management assurance to be useful it needs to be rigorous. Therefore, the approach needs to be supported by a standard, repeatable framework. The foundation for this framework is in the ability to model the fault management system integrated in the hardware and software avionics real-time system. Models can assist in assuring both functional and quality attribute requirements such as reliability. The Architecture Analysis and Design Language (AADL) is a Society of Automotive Engineers (SAE) standard notation (AS5506/1) for the modeling and analysis of real-time systems. AADL has been extended to model fault management behavior through the AADL Error Annex, also an SAE standard. At its core, the AADL Error Annex provides rules for how software and hardware components are allowed to propagate an error across the avionics real-time system modeled in AADL. Because a standard notation is being used, there is intrinsic confidence to the approach. This paper will explore how the assurance of software fault management can be applied in practice. First, it is important to briefly review AADL and the AADL Error Annex as well as common terminology related to software fault management. Next, the application of software fault management assurance will be discussed. The first step in this application is to understand the very basic (atomic) hardware and software faults that occur at the component level. This information can be collected in the form of a failure modes and effects analysis (FMEA). An analysis is required in order to evaluate the ability of the software fault management system to, at the very least, detect the symptoms. This analysis answers two fundamental questions. First, to what degree are faults visible to the avionics software? Second, to what degree does the avionics software handle these faults? This paper presents an example to demonstrate the assurance of software fault management. The software fault management assurance framework proposed in this paper utilizes a standard notation, coupled with a formal mechanism for modeling faults. This provides a rigorous foundation for analysis on the avionics software real-time system in a repeatable manner. Therefore a model based assurance activity of a software fault management system can successfully be applied.

Recently, significant progress has been made in the development of timed process algebras for the specification and analysis of real-time systems. This paper describes a timed process algebra called ACSR, which supports synchronous timed actions and asynchronous instantaneous events. Timed actions are used to represent the usage of resources and to model the passage of time. Events are used to capture synchronization between processes. To be able to specify real systems accurately, ACSR supports a notion of priority that can be used to arbitrate among timed actions competing for the use of resources and among events that are ready for synchronization. The paper also includes a brief overview of other timed process algebras and discusses similarities and differences between them and ACSR.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Integer octagonal constraints (a.k.a. Unit Two Variables Per Inequality or UTVPI integer constraints) constitute an interesting class of constraints for the representation and solution of integer problems in the fields of constraint programming and formal analysis and verification of software and hardware systems, since they couple algorithms having polynomial complexity with a relatively good expressive power. The main algorithms required for the manipulation of such constraints are the satisfiability check and the computation of the inferential closure of a set of constraints. The latter is called tight closure to mark the difference with the (incomplete) closure algorithm that does not exploit the integrality of the variables. In this paper we present and fully justify an O(n 3) algorithm to compute the tight closure of a set of UTVPI integer constraints.KeywordsInference RuleAbstract DomainBottom ElementInteger ConstraintClosure ProcedureThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Formal methods encompass a wide choice of techniques and tools for the specification, development, analysis, and verification of software and hardware systems. Formal methods are widely applied in industry, in activities ranging from the elicitation of requirements and the early design phases all the way to the deployment, configuration, and runtime monitoring of actual systems. Formal methods allow one to precisely specify the environment in which a system operates, the requirements and properties that the system should satisfy, the models of the system used during the various design steps, and the code embedded in the final implementation, as well as to express conformance relations between these specifications. We present a broad scope of successful applications of formal methods in industry, not limited to the well-known success stories from the safety-critical domain, like railways and other transportation systems, but also covering other areas such as lithography manufacturing and cloud security in e-commerce, to name but a few. We also report testimonies from a number of representatives from industry who, either directly or indirectly, use or have used formal methods in their industrial project endeavours. These persons are spread geographically, including Europe, Asia, North and South America, and the involved projects witness the large coverage of applications of formal methods, not limited to the safety-critical domain. We thus make a case for the importance of formal methods, and in particular of the capacity to abstract and mathematical reasoning that are taught as part of any formal methods course. These are fundamental Computer Science skills that graduates should profit from when working as computer scientists in industry, as confirmed by industry representatives.

The verification and validation of CFD software is of utmost importance for the reliability and hence for the success of CFD technology in industry. This paper discusses the relative importance, key elements, and some examples of: • Verification of numerical models and computer software; • Validation of solutions against benchmark data; and • Calibration of the models and analysis process. Out of these, the main emphasis is placed on verification. This is in light of the growing generality and complexity of CFD software (in response to continuously increasing expectations in industry). Finally, three key success factors for effective utilization of CFD technology are pointed out. These are: 1) Verifications and Validation of software; 2) Skills of the Users; and 3) Vision, and commitment of the manager (s).

Across the broad research field concerned with the analysis of computational systems, research endeavors are often categorized by the respective models under investigation. Algorithms and tools are usually developed for a specific model, hindering their applications to similar problems originating from other computational systems. A prominent example of such a situation is the area of formal verification and testing for hardware and software systems. The two research communities share common theoretical foundations and solving methods, including satisfiability, interpolation, and abstraction refinement. Nevertheless, it is often demanding for one community to benefit from the advancements of the other, as analyzers typically assume a particular input format. To bridge the gap between the hardware and software analysis, we propose Btor2C, a translator from word-level sequential circuits to C programs. We choose the Btor2 language as the input format for its simplicity and bit-precise semantics. It can be deemed as an intermediate representation tailored for analysis. Given a Btor2 circuit, Btor2C generates a behaviorally equivalent program in the language C, supported by many static program analyzers. We demonstrate the use cases of Btor2C by translating the benchmark set from the Hardware Model Checking Competitions into C programs and analyze them by tools from the Intl. Competitions on Software Verification and Testing. Our results show that software analyzers can complement hardware verifiers for enhanced quality assurance: For example, the software verifier VeriAbs with Btor2C as preprocessor found more bugs than the best hardware verifiers ABC and AVR in our experiment.

: This report summarizes a survey of published research in real time systems. Material is presented that provides an overview of the topic, focusing on communications protocols and scheduling techniques. It is noted that real-time systems deserve special attention separate from other areas because of the unique properties. This has not been the case in computer science and operations research until quite recently, resulting in the absence of formal tools for design and analysis of real-time systems. The early work on applications as well as notable theoretical advances are summarized. Descriptions of more recent work in the field from the mid-1980s to the present are also provided.

The on-going industrial trend towards high value sustainable manufacturing has led to the emergence of hybrid manufacturing processes and resources. This new generation of processes and resources combine the capabilities of a number of older technologies on a single platform. This increase in capability, however, comes at the cost of increasing complexity. Manufacturing processes, in general, can be categorised into subtractive processes, additive processes and transformative processes. While traditional machines supported a single type of these processes (e.g. a turn-mill machine that supports multiple metal removal - subtractive - processes), the new hybrid machines combine multiple types in one device. As a result, the current process and resource models have many shortcomings in representation of hybrid processes and hybrid machines. In this research formal methods are used to construct a new type of model for hybrid manufacturing processes. Formal methods are mathematically based techniques that allow clear and nonambiguous specification, development and, most importantly, verification of software and hardware systems. This paper utilises the ISO-standardised Z notation (named after Zermelo-Fraenkel set theory) to construct a formal model for hybrid manufacturing processes. The capabilities of the model in specification and verification of a hybrid device is then discussed through the use of a case study based on a prototype parallel kinematics hybrid manufacturing platform.

Formal methods in Computer Science are a particular kind of mathematically-based techniques for the specification, development and verification of software and hardware systems. Among them, Petri Nets have been widely used because of their high expressive power and accurate description capabilities. On the other hand, Dynamical Systems theory has not been used for these purposes so far. In this paper we present the first use of Discrete Dynamical Systems under the aim to better analyze Concurrent Computing Systems. In order to do that, Petri Nets, PNs, are properly encoded into DDSs, so defining the corresponding Phase Space with its metric structure and the evolution operator of the system.

This volume contains the proceedings of Infinity'12, the 14th International Workshop on Verification of Infinite-State Systems, which was held in Paris, France on the 27th of August 2012 as a satellite event of FM'12. The aim of the INFINITY workshop is to provide a forum for researchers interested in the development of formal methods and algorithmic techniques for the analysis of systems with infinitely many states, and their application in automated verification of complex software and hardware systems.

The task of checking if a computer system satisfies its timing specifications is extremely important. These systems are often used in critical applications where failure to meet a deadline can have serious or even fatal consequences. This paper presents an efficient method for performing this verification task. In the proposed method a real-time system is modeled by a state-transition graph represented by binary decision diagrams. Efficient symbolic algorithms exhaustively explore the state space to determine whether the system satisfies a given specification. In addition, our approach computes quantitative timing information such as minimum and maximum time delays between given events. These results provide insight into the behavior of the system and assist in the determination of its temporal correctness. The technique evaluates how well the system works or how seriously it fails, as opposed to only whether it works or not. Based on these techniques a verification tool called Verus has been constructed. It has been used in the verification of several industrial real-time systems such as the robotics system described below. This demonstrates that the method proposed is efficient enough to be used in real-world designs. The examples verified show how the information produced can assist in designing more efficient and reliable real-time systems.

Real-time multiprocessor systems have an increasing importance in current technology and are the source of innovations to build new applications that require high levels of computations (in for example, industrial processes, transportation, telecommunications, multimedia and medical equipment). In the context of real-time systems, it is not sufficient to prove the correctness of applications in term of results but also that those results are delivered in time. The following papers are extended, peer-reviewed, journal-versions of papers focusing on multiprocessor systems that have been selected by the conference program committee of the 19th Real-Time and Network Systems Conference (RTNS’2011) for their high quality. RTNS’2011 was held in Nantes, France in September 2011. The annual RTNS conference is mainly focused on the following topics: realtime system design and analysis; infrastructure and hardware for real-time systems; and real-time applications in the automotive, avionics, telecommunications, process control and the multimedia industries. Each paper was extended to add significant extra material and the resulting papers were re-reviewed and subject to the usual editorial process. The result is a special issue that we hope will be of interest to the real-time community. In recent years, multiprocessor architectures have become a firm favorite with the real-time community, and multicore processors are found in products ranging from small portable cell phones to large computer servers. New scheduling approaches

We present a new net-reduction methodology to facilitate the analysis of real-time systems using Delay Time Petri Nets (DTPNs). Net reduction is one of the most important techniques for reducing the state-explosion problem of Petri nets. However, the application of net reduction to current timed-extensions of Petri nets (such as Merlin's Time PNs) is very limited due to the difficulty faced in the preservation of timing constraints. To overcome this problem, we introduce DTPNs which are inspired by Merlin's (1976) Time PNs, Senac's (1994) Hierarchical Time Stream PNs, and Little's (1991) Timed PNs. We show that DTPNs are much more suitable for net reduction. Then, we present a new set of DTPN reduction rules for the analysis of schedule and deadlock analysis. Our work is distinct from the others since our goal is to analyze real-time systems and the reduction methods we propose preserve both timing properties (schedule) and deadlock. To evaluate our framework, we have implemented an automated analysis tool whose main functions include net reduction and class-graph generation. The experimental results show that our net-reduction methodology leads to a significant contribution to the efficient analysis of real-time systems.

Timing correctness of hard real-time systems is guaranteed by schedulability analysis and worst-case execution time (WCET) analysis of programs. Traditional WCET analysis mainly deals with application programs and has achieved success in industry. Timing analysis of application programs along cannot guarantee correctness of complete systems consisting RTOS. WCET tools designed for application program analysis have been applied to analyze RTOS routines by several research groups, but poor WCET estimations have been reported. Timing analysis of real-time systems considering both applications and RTOS has not been fully studied. So we intend to give a survey of related work on WCET analysis of RTOS. By summarizing previous work, challenges of WCET analysis of complete real-time systems are presented, and some possible further research potentials are unleashed.

Autonomous underwater vehicles (AUVs) have many, scientific, military, and commercial applications because of their potential capabilities and significant cost-performance improvements. Typical AUV development requires critical system design and many costly at-sea trials during which systems specifications can be validated. Modeling and simulation provides a cost-effective method for carrying out preliminary component or system (hardware and software) testing and verification. Due to the complexity of most AUV development and their tight schedules, the simulated systems often differ considerably from the actual embedded architecture, thereby reducing the fidelity of the entire simulation. We adopted a hardware-in-the-loop (HIL) simulation approach that includes some level of the system's hardware and software. As expected, an HIL simulation requires all components be run under hard real-time constraint. The paper presents our implementation and considerations on HIL simulation for single and multiple vehicles. A brief mention of sensor and environment modeling is also provided.