An Accurate Crosstalk Evaluation and Prediction Method for SiC MOSFET Considering Nonlinear Capacitance and Stray Parameters

A VDMOSFET structure with an additional p-region at the surface of the epitaxial layer is proposed. This structure realizes low reverse transfer capacitance without significantly degrading resistance. Reduction of the reverse transfer capacitance results in an improvement of the switching characteristics. The measured rise time is 49% and the fall time is 33% of the conventional VDMOSFET.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents a protection circuit for a fault under load (FUL). The protection circuit is characterized by the reverse transfer capacitance characteristic of IGBTs. The reverse transfer capacitance depends on the collector-emitter voltage and has a significant influence on the switching behavior under short-circuit conditions and normal conditions. An FUL is detected by monitoring a gate current because the current flows through the reverse transfer capacitance of IGBTs from the collector terminal to the gate terminal under FUL conditions. A physics-based IGBT model shows high accuracy for both static and dynamic characteristics, making it useful for developing a protection circuit for IGBTs subjected to short-circuit conditions. Simulated results using the physics-based IGBT model and experimental results verify the validity of the proposed protection circuit.

The Gallium Nitride high electron mobility transistor (GaN HEMT) has been considered as a potential power semiconductor device for high switching speed and high power density application since its commercialization. Compared with the traditional Si transistors, GaN HEMT has faster switching speed and lower on-off loss. As a result, it is more sensitive to the nonlinear parameters due to the fast switching speed. The subsequent voltage and current overshooting will affect the efficiency and safety of the GaN HEMT and power electronic systems. In this paper, an accurate switching transient analytical model for GaN HEMT is proposed, which considers the effects of parasitic inductances, nonlinear junction capacitances and nonlinear transconductance. The model characteristic of turn-ON process and turn-OFF process is illustrated in detail, and the equivalent circuits are derived for each switching transition. The accuracy of the proposed model can be verified by comparing the predicted switching waveform and switching loss with that of the experimental results based on the double pulse test (DPT) circuit. Compared with the conventional model, the proposed model is more accurate and matches better with the experimental results than the conventional model. Finally, this model can be used for analyzing the influences of gate resistance, nonlinear junction capacitances, and parasitic inductances on switching transient waveform and refining calculation switching loss.

Bidirectional, or four-quadrant switches (FQS)\ncan be designed as back-to-back MOSFETs connected in\ncommon-drain (CD) or common-source (CS) topologies. CDFQS and CS-FQS assembled from discrete 1.2 kV commercially\navailable SiC power MOSFETs were characterized to obtain\ncapacitance and switching loss values. The CD-FQS exhibited a\n1.17x larger turn-on loss compared to the CS-FQS, while the\nCS-FQS exhibited a 1.52x larger turn-off loss compared to the\nCD-FQS. The CS-FQS exhibited a lower input capacitance,\nwhile the CD-FQS exhibited a lower output and reverse transfer\ncapacitance.

A new silicon carbide (SiC) enhancement-mode lateral channel vertical junction fieldeffect transistor (LC-VJFET), namely “source inserted double-gate structure (SID-gate) with a supplementary highly doped region (SHDR)”, was proposed for achieving extremely low power losses in high power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LCVJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20 % reduction in on-state loss (Pon) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (Psw) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75 % ~ 95 % reduction, by significantly reducing both input capacitance (Ciss) and reverse transfer capacitance (Crss) of the device.

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( ${C}_{rss})$ . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher ${C}_{{{\text {rss}}}}$ and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic ${R}_{{ \mathrm{ON}}}$ during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high ${V}_{{{\text {DS}}}}$ , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high ${V}_{{{\text {DS}}}}$ is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained.

Effects of gamma-ray irradiation on thin-gate-oxide VDMOSFET characteristics are described. The gate-oxide thickness of the device is 34 nm. The device has a radiation tolerance of 2*10/sup 5/ rad, which is four times higher than that of 100-nm gate-oxide device. Although the thin gate oxide increases input capacitance, reverse transfer capacitance is reduced by using the VDMOSFET cell structure with an additional p region. The VDMOSFET is suitable as a switching device for high-frequency switching power supplies used in communication satellites. >

An improved SiC MOSFET model is proposed in this article, which predicts the dynamics accurately in the wide operation range of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . The temperature-sensitive effect (TSE), the short channel effect (SCE), and the interface state effect are comprehensively taken into consideration in the modeling of the transfer characteristics. A dynamic test platform of transfer characteristics is designed to extract data better than the datasheet. The turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> processes of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> are decoupled, and the nonlinear interterminal capacitances are also modeled thoroughly. To verify the convergence and accuracy of the proposed model, a 400 V/30 A double pulse test is fulfilled, and the complex converters are also simulated with the proposed model. The results show that the proposed model has good convergence and accuracy in predicting the switching trajectory of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> , which would be favorable for observing the dynamics in the high-speed switching processes of the SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> .

The paper presents a compact simulation program with integrated circuit emphasis (SPICE) model for a 1200V/19A Silicon Carbide power metallic oxide semiconductor field effect transistor (MOSFET). Based on an equivalent circuit topology, the model completely describes the static and dynamic device characteristics which include the MOSFET channel current, the nonlinear junction capacitance and the switching behavior. Especially the parasitic elements effect is also considered and studied during the modeling, testing and simulation. The model parameters are extracted based on the experimental measurement data. For convenience, the model is implemented by Verilog-A description language and embedded in the simulation software – Advanced Design System (ADS). The validity and accuracy of the model are validated by the double pulse test under inductor load. The Verification result shows that the modeling job is correct and available for prediction of the switching performance under different conditions.

This article explores the high-frequency characteristics of gallium nitride (GaN) power-switching devices and evaluates their application performance using a double-pulse test (DPT) circuit model. With the increasing adoption of GaN power-switching devices in high-performance and miniaturized electronic products, their low junction capacitance makes them highly suitable for high-frequency applications. However, parasitic inductance in the power loop can introduce resonance phenomena, impacting system stability and switching performance. To address this, this study integrates the parasitic parameters of printed circuit boards (PCBs) with the nonlinear junction capacitance characteristics of GaN devices. Finite element analysis (FEA) is employed to extract PCB parasitic inductance values and analyze their effects on GaN power-switching behavior. The findings indicate that precise extraction and analysis of parasitic inductance are critical for optimizing the performance of GaN switching devices. Additionally, this study investigates mitigation strategies to minimize parasitic inductance, ultimately enhancing GaN device design and reliability. The insights from this research provide valuable guidance for the development of GaN power devices in high-frequency applications.

Nanosecond output pulse and high efficiency are achieved in high-voltage pulsed power supplies (HVPPSs) by applying silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s), whose switching speed and switching loss are two vital characteristic parameters. However, the existing research on switching characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is mainly based on the double pulse test circuits with inductive loads, which is not suitable for assessing the devices in HVPPSs with resistive loads. Besides, some simplified analytical methods in HVPPSs lead to poor precision. To accurately predict the switching behavior of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s in HVPPSs for guiding the design of gate driving circuits and power loops, this article proposes an accurate analytical model considering parasitic inductances, nonlinear parasitic capacitances, transfer characteristic, and output characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. High-precision fitting of transfer characteristic is realized by using the Gaussian function. Besides, the dynamic parasitic gate-drain capacitance is measured by experiment, and three-dimensional curve fitting is performed on the output characteristics to exactly represent <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -resistance. Furthermore, switching speed and switching loss can be directly calculated according to the solved state variables. Finally, the analytical model is verified by experiment, and the effects of gate driving circuits and power loops on switching characteristics are researched in detail.

Accurate nonlinear capacitance measurement methods play an important role in the modeling of silicon carbide (SiC) MOSFET for transient switching analysis and design of high performance power electronics equipment. This paper presents an improved capacitance measurement method, which can obtain the transfer capacitance Crss of SiC MOSFET accurately. This method is based on the time-domain reflectometry theory during dynamic switching process, which is easy to design and be captured. Different from other existing methods, the influence of gate-drain stray capacitance caused by PCB wiring and probes is considered in the process of measurement, thus resulting in the minimization of errors produced by instrument and layout. Also, the impact of parasitic inductance in driver loop on measurement results can be counteract skillfully. In addition, the proposed method characterized by dynamic behavior can be used in high-voltage applications. The performance of this proposed method is verified and compared experimentally by a double-pulse test (DPT) platform.

Among a variety of applications of organometallic compounds, their use as MOCVD precursors is one of the most extensive areas. To our minds, one of the most powerful and accurate methods for evaluation and prediction of thermal behaviour of the precursor is mass-spectrometry coupled with mass-analyzed ion kinetic energy spectrometry. Traditionally, both structure and composition of deposited materials and the precursor's thermal decomposition channels were controlled by gas-phase composition, the process temperature and pressure, i.e. by extemal factors. A possibility of such a control via inner factors - i.e. structure of a specially designed precursors is demonstrated for a series of new mixed-ligand organometallic compounds of In, Zr and Hf.

Chapter 5 - Stray parameters of the measuring system and ways of defining them

In high-power converters based on SiC-MOSFET half-bridge modules, laminated busbar plays a critical role in linking the DC capacitor bank to power modules. The busbar stray capacitance has the same order of magnitude with drain-source capacitance of SiC-MOSFET and has a great impact on the turn-off voltage oscillation of SiC-MOSFET. In this paper, parasitic elements of a three-layer laminated busbar are extracted and a busbar model with consideration of stray capacitance is obtained. A spectrum analysis is performed on a small-signal model of equivalent circuit of double pulse test (DPT), and the model with busbar stray capacitance has lower oscillation frequency of turn-off voltage. The results of simulation and experiment of DPT indicate that the simulation waveforms of model with busbar stray capacitance are more consistent with the experimental waveforms over the entire voltage levels, which proves a greater accuracy of the proposed busbar model.