An Adaptive All-Pass Filter for Time-Varying Delay Estimation

PurposeTraditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.Design/methodology/approachRather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.FindingsAn ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.Originality/valueA software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

Digital filters play a central role in modern Digital Signal Processing (DSP) systems. Finite Impulse Response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Digital filters play a central role in modern digital signal processing (DSP) systems. Finite impulse response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

WITHDRAWN: An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

Background/Objectives: FIR filters play a vital role in signal processing applications. This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design. Methods/Statistical Analysis: The proposed FIR filter is designed using buffer based DA and it is simulated and synthesized using Cadence digital labs. This is compared with different architectures such as conventional DA, separated look up table DA and LUT less DA. Findings: Synthesis report shows that the proposed design has 52% less power dissipation compared with the conventional DA, 21% reduction in delay with separated Look Up Table (LUT) DA and 8% reduction in area with LUT less DA. Conclusion/Improvements: Presently this method is applied for ECG signal input with 16-tap FIR filter. This can be extended for higher order filters to achieve better performance.

In Digital wireless communication system Finite Impulse Response (FIR) filter is used fundamentally pipelined as well as support Multiplication with Accumulation scheme (MAC) that results in important save of calculation. Efficient area along with delay recognition of great order FIR filters for update applications have been achieved by the opportunity of recognition of block FIR filter in transpose form organization. The projected transpose form block filter of update applications are developed by a general carry select adder based architecture. Secured digital FIR filter block is implemented by a pepped-up design using the MAC scheme. Booth multiplier has been used in MAC scheme. The proposed method has less area also delay than conventional filter.

The paper presents the design and implementation of a high speed digital Finite Impulse Response (FIR) filter using unfolding transformation technique. FIR Filter has widespread applications in signal processing such as image processing, biomedical signal processing, high speed communication systems, noise elimination and many more. The speed of FIR filter can be improved with high speed vedic multiplier and with low propagation delay carry increment adder. In the proposed design, the FIR filter is unfolded by a factor 3 which results in scheduling the filter to a smaller iteration period and along with this throughput of the filter also increases. The propagation delay is reduced to almost three times in FIR filter by using faster adder, high speed multiplier and unfolding transformation technique. We have synthesized the proposed design on Xilinx ISE 14.7 with Virtex IV FPGA family. The obtained results also confirm the faster performance of the FIR filter.

A mixed signal processing circuit includes an analog to PWM converting circuit and a finite impulse response (FIR) filter having a multiple output tapped delay line and a summing and integration circuit. The mixed signal processing circuit converts an input analog signal to a PWM signal, forms a multi-level PWM signal from the PWM signal and one or more delayed versions of the PWM signal, and converts the multi-level PWM signal to an output analog signal. The analog to PWM converting circuit is implemented using a triangle waveform generator and a comparator. The FIR filter is implement using a resistive network to apply scaling coefficients of the FIR filter. The mixed signal processing circuit can be implemented within a noise cancellation headphone to generate a noise cancelling signal or generally in applications that would be benefitted from the combination of analog input/output and digital filter techniques.

Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity.

: Finite impulse response (FIR) filters are widely used in various DSP applications. The low-power or low-area techniques developed specifically for digital filters can be found in. Many applications in digital communication (channel equalization, frequency channelization), speech processing (adaptive noise cancelation), seismic signal processing (noise elimination), and several other areas of signal processing require large order FIR filters ,since the number of multiply - accumulate (MAC) operations required per filter output increases linearly with th e filter order, real - time implementation of these filters of large orders is a challenging task. This paper presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter these methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to fir filters to power consumption reduced thus reduce power consumption due to glitches is also reduced. This paper is implemented using XILINX ISE and hardware used is Spartan-3E and family is XC2S200E.

In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on systolic array architecture with parallel data processing units is presented. A high level of parallelism is observed in the proposed work, improving the efficiency of variable coefficient FIR structure. The parallel look-up tables (LUT) in combination with the shift accumulator emulate multiply and accumulate operations. In order to reduce the number of clock cycles, B parallel LUTs are used, where B is the coefficient size. The block processing in BLMS Adaptive FIR Filter of block length L gives L times high throughput. This structure accepts block of input samples and generates block of output in each clock cycle. It requires less number of registers for computing filter output response and weight increment vector as memory reuse concept is used for implementing registers. This structure doesn’t require multiplexer. The designed DA based FIR filter is implemented on FPGA. The implementation results shows that the manuscript presents a high speed and low power architecture. The proposed structure provides 17.3 times less power and 9.5 times increase in throughput when compared to existing designs.

Chapter 2 - Design and Implementation of Digital FIR Filters

An Finite Impulse Response (FIR) filter is a widely used digital filter technology whose impulse response has a finite duration. An FIR filter is usually favored for many reasons such as easy to design, easy to implement on a variety of system architectures. An FIR filter can be easily designed with a linear phase response and its output is more predictable since it doesn't have feedback components. There are both engineer and mathematical methods for designing an FIR filter so that machine learning doesn't play an important role in the FIR filter design. In this paper, we present an alternative to traditional filter design methods to direct learn the FIR filter coefficients from input data with machine learning algorithm. With the proposed algorithm, we can easily design an FIR filter from the input data mixed with designed all spectrum noise signal. To show the capability of this algorithm, an example application of suppressing background music from speech or vice versa is demonstrated in this paper. Despite that the music and speech have a lot of overlap in their spectrum, the filter designed by our algorithm can successfully suppress music or speech in a mixture of music and speech signals.

The Cook-Toom algorithm is widely used in short-length linear convolution, which is the building block of large points convolution algorithms. This paper proposes improved parallel finite impulse response (FIR) filter structures for linear-phase FIR filter, which is based on the Cook-Toom algorithm. In the proposed structures, Cook-Toom algorithm is used to reduce the number of sub-filters, and the symmetric properties of the linear-phase FIR filter's coefficients is used to further reduce the number of multipliers in sub-filters. Compared with the reported FFA and ISCA parallel FIR filter structures, the proposed method can substantially reduce the computational complexity. Specifically, for a 8-parallel 144-tap filter, the proposed design saves 18 multipliers (5%), 45 adders (7.9%) compared with the structure based on Winograd convolution algorithm [7].