2- https://doi.org/10.1145/255305.255313
An algorithm for microcode compaction of VHDL behavioral descriptions
- Jan 1, 1987
- J Bhasker
Abstract
We present an algorithm to transform a sequential (vertical microcode) VHDL (VHSIC Hardware Description Language) behavioral description of a digital system design into a parallel (horizontal microcode) VHDL description. Data dependency analysis is performed on the sequential code to identify the parallelism within the code. This parallel VHDL code is targeted for synthesis by the MIMOLA synthesis system.
- # VHSIC Hardware Description Language
- # Horizontal Microcode
- # Data Dependency Analysis
- # Description Of System Design
- # Digital Design
- # Parallel Code
- # VHSIC Hardware Description Language Code
- # Digital System Design
- # Hardware Description Language
- # Sequential Code
