An asymptotically optimal algorithm for gate array placement

The inventory -routing problem is a NP hard problem. It is difficult to find the optimal solution in polynomial time. Many scholars have studied it in many years. This paper analyses the inventory-routing optimisation problem, and comprehensive differential evolution algorithm is good performance in solving combinatorial optimisation problems. The differential evolution algorithm was improved to make it be suitable for solving discrete combination optimisation problems. In order to improve the performance of the differential evolution algorithm to solve the inventory routing problem, this paper puts forward dynamic adjustment of mutation factor and crossover factor of the differential evolution. It is proved by numerical experiments that the proposed algorithm has certain performance advantages, and it also proves that the improved algorithm can improve the performance of the algorithm by dynamic adjustment of the mutation factor and crossover factor.

Local search algorithms for combinatorial optimization problems are in general of pseudopolynomial running time and polynomial-time algorithms are often not known for finding locally optimal solutions for NP-hard optimization problems. We introduce the concept of epsilon-local optimality and show that an epsilon-local optimum can be identified in time polynomial in the problem size and 1/epsilon whenever the corresponding neighborhood can be searched in polynomial time, for epsilon > 0. If the neighborhood can be searched in polynomial time for a delta-local optimum, we present an algorithm that produces a (delta+epsilon)-local optimum in time polynomial in the problem size and 1/epsilon. As a consequence, a combinatorial optimization problem has a fully polynomial-time approximation scheme if and only if it has a fully polynomial-time augmentation schem

This paper considers two-dimensional (2-D) retiming, which is the problem of retiming circuits that operate on 2-D signals. We begin by discussing two types of parallelism available in 2-D data processing, which we call inter-iteration parallelism and inter-operation parallelism. We then present two novel techniques for 2-D retiming that can be used to extract inter-operation parallelism. These two techniques are designed to minimize the amount of memory required to implement a 2-D data-flow graph while maintaining a desired clock rate for the circuit. The first technique is based on an integer linear programming (ILP) formulation of the problem, and is called ILP 2-D retiming. This technique considers the entire 2-D retiming problem as a whole, but long central processing unit times are required if the circuit is large. The second technique, called orthogonal 2-D retiming, is a linear programming formulation which is derived by partitioning ILP 2-D retiming into two parts called s- and a-retiming. This technique finds a solution in polynomial time and is much faster than the ILP 2-D retiming technique, but the two sub problems (s- and a-retiming) can give results which are not compatible with one another. To solve this incompatibility problem, a variation of orthogonal 2-D retiming called integer orthogonal 2-D retiming is developed. This technique runs in polynomial time and the s-retiming and a-retiming steps are guaranteed to give compatible results. We show that the techniques presented in this paper can result in memory hardware savings of 50% compared to previously published 2-D retiming techniques.

The min-rank of a graph was introduced by Haemers (Algebr. Methods Graph Theory 25:267–272, 1978) to bound the Shannon capacity of a graph. This parameter of a graph has recently gained much more attention from the research community after the work of Bar-Yossef et al. (in Proceedings of the 47th Annual IEEE Symposium on Foundations of Computer Science (FOCS), pp. 197–206, 2006). In their paper, it was shown that the min-rank of a graph \(\mathcal {G}\) characterizes the optimal scalar linear solution of an instance of the Index Coding with Side Information (ICSI) problem described by the graph \(\mathcal {G}\).It was shown by Peeters (Combinatorica 16(3):417–431, 1996) that computing the min-rank of a general graph is an NP-hard problem. There are very few known families of graphs whose min-ranks can be found in polynomial time. In this work, we introduce a new family of graphs with efficiently computed min-ranks. Specifically, we establish a polynomial time dynamic programming algorithm to compute the min-ranks of graphs having simple tree structures. Intuitively, such graphs are obtained by gluing together, in a tree-like structure, any set of graphs for which the min-ranks can be determined in polynomial time. A polynomial time algorithm to recognize such graphs is also proposed.

Existing research on a simultaneous wireless information and power transfer (SWIPT) system is based on the assumption of Gaussian inputs. However, the optimal design on Gaussian inputs may lead to dramatic performance loss for practical systems with finite-alphabet inputs. This paper focuses on the precoder design for a SWIPT system with finite-alphabet inputs and instantaneous channel state information over a multiple-input multiple-output channel. We formulate the optimal precoder design as an optimization problem, in which the objective is to maximize the mutual information over the channel from the transmitter to the information receiver under the constraints of transmit power and harvested energy threshold. The formulated problem is NP-hard, so a global optimal solution cannot be found within the polynomial time. The main contributions of this paper are as follows: 1) By using its structure, the NP-hard problem is relaxed to a semidefinite programming problem. Then, a general solving framework for both co-located and separated receiver cases, based on the semidefinite relaxation (SDR) technique, is developed to achieve a near optimal precoder. 2) For the case of co-located receivers, we show that the optimal precoder design is a concave problem with respect to power allocation; then, a specific algorithm for co-located receivers is proposed. Compared with the general SDR-based method, the specific algorithm for co-located receivers exhibits almost the same performance but much lower complexity. 3) The performance of several practical co-located receiver designs is analyzed in SWIPT systems with finite-alphabet inputs. Finally, we provide simulation results to show the efficacy of the proposed algorithms.

A hundred fold performance improvement of a CAD tool can bring about a similar increase in design size. Hardware accelerators for CAD tools offer such performance improvements, but are application specific. Though some accelerators can be programmed to adapt themselves to somewhat different applications, it takes as much time and money to reconfigure one as it does to purchase a new one. Hence the use and acceptance of hardware accelerators has been limited. To alleviate the above mentioned problem we demonstrate that a wide variety of problems in VLSI design, viz gate array placement, standard cell placement, PLA folding, channel routing can be mapped on to a single mother problem. From the solution to the mother problem, the solutions to the other problems can be deduced. Therefore, a single hardware accelerator to solve the afore mentioned mother problem along with a translator-deducer kernel to translate the various problems to the mother problem and again decipher the solution would be sufficient to ...

The capacitated vehicle routing problem (CVRP) is regarded as an NP-hard problem. Moreover, the CVRP is described as a model that can be used in many applications such as transport, logistics, and distribution. The exact algorithms can find exact optimal solutions on the small-sized problem instances; however, for large-sized instances it is difficult to find the exact optimal solutions in polynomial time. This reason motivated the researchers to present heuristic/metaheuristic algorithms to solve large-sized problem instances within a reasonable computational time. One of the good algorithms that deal with the CVRP is the ant colony optimization (ACO) algorithm. Several ACO algorithms have been suggested in the literature, such as the ant system (AS) algorithm, ant colony system (ACS) algorithm, and so on. On the other hand, ACO is designed to solve the path problem that finds the best way. However, this algorithm still lacks exploratory mechanisms, which results in premature convergence and stagnation issues. Therefore, we propose to develop an enhanced ACS (EACS) algorithm for solving the CVRP based on subpaths. In our proposed algorithm, we propose to utilize the K-nearest neighbour (KNN) algorithm for finding the best initial solution and then enhance the diversity mechanism of the proposed algorithm by avoiding the generation of the same solution using subpaths. This uses the diversity of the generated solution to find a better solution with a shorter route in a reasonable amount of computational time. Furthermore, we propose to apply the three-opt algorithm to the completed subtour and the k-opt algorithm to the subpath gained from the experience of the subpath. Finally, to verify the effectiveness of the proposed EACS algorithm, the algorithm is tested on some CVRP instances and is compared with one of the state-of-the-art methods, namely, the enhanced simulated annealing algorithm. The comparative study showed a better performance of our EACS compared to the enhanced simulated annealing algorithm.

We consider the classic scheduling problem of minimizing the total weighted flow-time on a single machine (min-WPFT), when preemption is allowed. In this problem, we are given a set of $n$ jobs, each job having a release time $r_j$, a processing time $p_j$, and a weight $w_j$. The flow-time of a job is defined as the amount of time the job spends in the system before it completes; that is, $F_j = C_j - r_j$, where $C_j$ is the completion time of job. The objective is to minimize the total weighted flow-time of jobs. This NP-hard problem has been studied quite extensively for decades. In a recent breakthrough, Batra, Garg, and Kumar presented a {\em pseudo-polynomial} time algorithm that has an $O(1)$ approximation ratio. The design of a truly polynomial time algorithm, however, remained an open problem. In this paper, we show a transformation from pseudo-polynomial time algorithms to polynomial time algorithms in the context of min-WPFT. Our result combined with the result of Batra, Garg, and Kumar settles the long standing conjecture that there is a polynomial time algorithm with $O(1)$-approximation for min-WPFT.

This paper presents a novel mathematical model of a closed-loop layout problem with unequal-sized facilities. This problem belongs to a class of combinatorial optimization and NP-hard problems. Obtaining an optimal solution for this complex, large-sized problem in reasonable computational time by using traditional approaches and is extremely difficult. Therefore, we propose three well-known meta-heuristics, namely genetic algorithm (GA), ant colony optimization (ACO), and simulated annealing (SA), to solve the closed-loop layout problem. These algorithms report near-optimal and promising solutions in a short period of time because of their efficiency. The computational results obtained by these algorithms are compared with the results reported by the Lingo 8.0 software package. Finally among our three proposed meta-heuristics, the output of SA is better than other two algorithms and the Lingo.

This paper contributes to the problem of deterministic localization of robot networks using local and relative observations only. This is an important issue in collective and cooperative robotics where global positioning systems are not available, and the basic premise is the localization ability of the group. We prove that, giving a set of relative observations made by the robots, the unique non ambiguous pose estimation of the robot network in a deterministic way, is a NP-hard problem. This means that no polynomial-time algorithm can deterministically solve the unique pose estimation problem based on relative observations. The consequence is that no guaranty can be provided, in a polynomial time, that the possibly estimated poses of the robots, will correspond to the effective (actual) ones. The proof is based on complexity theory. We build appropriate polynomial-time reductions acting on the localization problem and leading to well known NP-hard problems. The paper gives some tracks to overcome this issue.

An effective zero-inventory-ordering policy for a single-warehouse multiple retailer problem with a modified all-unit discount

<p><span>Travelling salesman problem is a well researched problem in computer science and has many practical applications. It is classified as a NP-hard problem as its exact solution can only be obtained in exponential time unless P = NP. There are different variants of the travelling salesman problem (TSP) and in this paper, asymmetric travelling salesman problem is addressed since this variant is quite often observed in real world scenarios. There are a number of heuristic approaches to this problem which provides approximate solutions in polynomial time, however this paper proposes an exact optimal solution which is accelerated with the help of multi-threading-based parallelization. In order to find the exact optimal solution, we have used the held-karp algorithm involving dynamic programming and to reduce the time taken to find the optimal path, we have used a multi-threaded approach to parallelize the processing of sub-problems by leveraging the central processing unit cores (CPUs). This method is an extension of a well researched solution to the TSP; however, this method shows that solutions to computationally intensive problems involving sub-problems such as the asymmetic travelling salesman problem (ATSP) can be accelerated with the help of modern CPUs.</span></p>

Fine granularity resource allocation of virtual data center with consideration of virtual switches

Recently, the nature has become a source of inspiration for the creation of many algorithms. A great research effort has been devoted to the development of new metaheuristics, especially nature-inspired one to solve numerous difficult combinatorial problems appearing in various industrial, economic, and scientific domains. The nature-inspired algorithms offer additional advantages over classical algorithms; they seek to find acceptable results within a reasonable time, rather than an ability to guarantee the optimal or sub-optimal solution. The travelling salesman problem (TSP) is an important issue in the class of combinatorial optimization problem and also classified as NP-hard problem and no polynomial time algorithm is known to solve it. Based on three nature-inspired algorithms, this paper proposes a comparative study to solve TSP. The proposed algorithms are evaluated on a set of symmetric benchmark instances from the TSPLIB library.

Simulated annealing was first introduced in 1983 as a generic stochastic algorithmic approach to solve optimization Prof. C. L. Liu and his students H. W. Leong and D. F. Wong were among the earliest EDA researchers who applied simulated annealing to EDA. They solved a wide range of EDA problems with successes and reported their results in a series of papers at premier EDA conferences such DAC and ICCAD. Liu, Leong, and Wong later summarized their works in a research monograph entitled Simulated Annealing for VLSI Design, published in 1988 by Kluwer Academic Publishers. In the Preface of their book, the authors wrote We hope that our experiences with the we employed, some of which indeed bear certain for different problems, could be useful as hints and guides for other researchers in applying the method to the solutions of other problems. Indeed, there were similarities in techniques among Liu's works that had influenced the design of simulated annealing EDA algorithms in the past 20 some years. To better understand Liu's contributions in simulated annealing, one should note that a typical simulated annealing algorithm uses a solution space and a cost function that come directly with the problem. Although computation time may be high, the algorithm is straightforward to design, making simulated annealing an attractive option for difficult problems where clever algorithms are hard to come by. On the contrary, Liu's simulated annealing algorithms have a completely different style: They resemble clever algorithms that attempt to solve difficult problems in polynomial time, and they often have a strong algorithmic flavor with a significant effort spent on optimizing the solution space and cost function. In this talk, we will discuss Prof. Liu's pioneering contributions in simulated annealing for EDA.