An efficiency model for general purpose instruction level parallel architectures in image processing

As wireless video products evolve, they demand more sophisticated processing at higher resolutions and frame rates. Computational performance and energy efficiency have become critical design issues. This paper presents the Quantized Color Pack eXtension (QCPX) combined with a loop unrolling (LU) technique to improve execution performance and energy efficiency of color image and video processing applications. QCPX applied to a 32-bit datapath processor supports parallel operations on two packed 16-bit YCbCr (Y: luminance, Cr and Cb: chrominance) color pixels, providing greater subword-level parallelism by increasing the number of smaller color pixels packed into a word. Instruction-level parallelism can be further enhanced through loop unrolling. These techniques provide greater performance and efficiency for multimedia workloads on mobile systems. Experimental results on a set of media benchmark applications indicate that the LU plus QCPX-optimized version achieves a speedup ranging from 3.8 to 7.9 while reducing the energy consumption from 76% to 87% over the baseline version on identically configured, dynamically scheduled ILP superscalar processors. The LU plus QCPX-optimized version also outperforms the LU plus MDMX-like (MIPS’s multimedia extension) version.

Exploitation of instruction-level parallelism is an effective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be applied to increase instruction-level parallelism. This paper describes and evaluates a software technique, dynamic memory disambiguation, that permits loops containing loads and stores to be scheduled more aggressively, thereby exposing more instruction-level parallelism. The results of our evaluation show that when dynamic memory disambiguation is applied in conjunction with loop unrolling, register renaming, and static memory disambiguation, the ILP of memory-intensive benchmarks can be increased by as much as 300 percent over loops where dynamic memory disambiguation is not performed. Our measurements also indicate that for the programs that benefit the most from these optimizations, the register usage does not exceed the number of registers on mast high-performance processors.

Finding a vast array of applications, the problem of computing the convex hull of a set of sorted points in the plane is one of the fundamental tasks in pattern recognition, morphology and image processing. The main contribution of this paper is to show a simple parallel algorithm for computing the convex hull of a set of n sorted points in the plane and evaluate the performance on the dual quad-core processors. The experimental results show that, our implementation achieves a speed-up factor of approximately 7 using 8 processors. Since the speed-up factor of more than 8 is not possible, our parallel implementation for computing the convex hull is close to optimal. Also, for 2 or 4 processors, we achieved a super linear speed up.

Edge detection is one of the most important tasks in image processing and pattern recognition. Edge detector with multiple color channels can provide more edge information. However, the uncertainty occurring with the edge detection in each single channel and the discordance existing in the fusion of multiple channels edge detectors make the detection difficult. In this paper, we propose a new edge detection method in color images based on information fusion. We show that obtaining final edge through fusing the edge information in each channel is a challenging problem to make decision in the framework of Multi-Criteria decision making (MCDM). In this work, we propose to detect edges in color images using Cautious OWA with evidential reasoning (COWA-ER) and Fuzzy-Cautious OWA with evidential reasoning (FCOWA-ER) to handle the uncertainty and discordance. Experimental results show that the proposed approaches achieve better edge detection performance compared with the original edge detector.

EPIC architectures rely heavily on state-of-the-art compiler technology to deliver optimal performance while keeping hardware design simple. It is generally believed that an optimizing compiler has an enormous scheduling window to exploit instruction-level parallelism (ILP) since the compiler orchestrates the entire program. Many state-of-the-art compilers typically confine optimizations to loop boundaries (e.g. software pipelining, trace scheduling, and loop unrolling) and function boundaries (e.g. loop peeling, loop exchanges, invariant hoisting, and global optimizations). Although techniques such as function inlining and interprocedural optimizations can alleviate these constraints to a limited extent, loop and function boundaries are often the real scopes of the compiler scheduler. Several previous ILP studies have explored the limits of parallelism on dynamic superscalar machines; however, those results are not applicable to EPIC architectures since they rely on dynamic scheduling, not static code scheduling by the compiler, to reorder instructions. In this paper, we evaluate the limits in ILP obtained through compiler scheduling alone. We quantify these limits as more restrictive scheduling constraints are imposed-starting from inter-procedural code scheduling, to intra-procedural and finally to loop-confined code scheduling.

Hardware support for image processing is very important in emerging applications such as desktop publishing, medical imaging, and multimedia. In the past, computational needs for intensive image processing tasks, such as image analysis of satellite data and pattern recognition, were satisfied with custom, complex, and expensive image processing architectures [1], [2] However, the latest scientific workstations have enough compute power for low-cost desktop image processing. Furthermore, traditional image processing operations, such as texture mapping and warping, are now combined with conventional graphics techniques. Hence, there is an increased interest for accelerated image and video processing on low cost computational platforms, such as personal computers and scientific workstations.

While in the last decade image and video processing (IVP) have gradually moved from special purpose computer architectures based on massive parallelism (MP) to general purpose computer architectures based on instruction-level parallelism (ILP), a new challenge is now to be faced by the IVP community, namely the application of IVP also in small-size embedded systems (e.g., video players, smart cameras, digital diaries, etc.) based on ILP processors. Because of the requirements of low size, weight, and power consumption, these embedded systems do not take advantage of processors that feature advanced dynamic code optimization mechanisms such as those based on instruction reordering and register renaming. On the other hand, the compile time techniques of present generation compilers do not appear to be aggressive enough to exploit the massive parallelism of IVP tasks in ILP architectures, thus leading to inefficient programs. This paper analyzes the efficiency of IVP programs on ILP CPUs. In particular it presents: (1) a reference model for the efficient design and implementation of highly parallel programs, such as the ones of the IVP domain; (2) an analysis of the inefficiencies of IVP programs implemented on ILP processors; and (3) a set of techniques, deriving from the reference model, that overcome these inefficiencies. These techniques are based on a novel computing paradigm called bucket processing.

: Many of today's high-performance computer processors are super-scalar. They can dispatch multiple instructions per cycle and, hence, provide what is commonly referred to as instruction-level parallelism. This super-scalar capability, combined with software pipelining, can increase processor throughput dramatically. Achieving maximum throughput, however, is nontrivial. Compilers must engage in aggressive optimization techniques, such as loop unrolling, speculative code motion, etc., to structure code to take full advantage of the underlying computer architecture. The phase-ordering implications of these optimizations are not well understood and are the subject of continuing research. Of particular interest are optimizations that enhance instruction-level parallelism. Two of these are loop unrolling and loop fusion. These are source-level optimizations that can be performed by either the programmer or the compiler. These optimizations have dramatic effects on the compiler's instruction scheduler. Performed too aggressively, these optimizations can increase register pressure and result in costly memory references. This paper details experiments performed to measure the effects of these source-level code transformations and how they influenced register pressure and code performance.

With increasing demands for performance by embedded systems, especially by digital signal processing (DSP) applications, embedded processors must increase available instructionlevel parallelism (ILP) within significant constraints on power consumption and chip cost. Unfortunately, supporting a large amount of ILP on a processor while maintaining a single register file increases chip cost and potentially decreases overall performance due to increased cycle time. To address this problem, some modern embedded processors partition the register file into multiple low-ported register files, each directly connected with one or more functional units. These functional unit/register file groups are called clusters. Clustered VLIW (very long instruction word) architectures need extra copy operations or delays to transfer values among clusters. To take advantage of clustered architectures, the compiler must expose parallelism for maximal functional-unit utilization, and schedule instructions to reduce intercluster communication overhead. High-level loop transformations offer an excellent opportunity to enhance the abilities of low-level optimizers to generate code for clustered architectures. This dissertation investigates the effects of three loop transformations, i.e., loop fusion, loop unrolling, and unroll-and-jam, on clustered VLIW architectures. The objective is to achieve high performance with low communication overhead. This dissertation discusses the following techniques: Loop Fusion This research examines the impact of loop fusion on clustered architectures. A metric based upon communication costs for guiding loop fusion is developed and tested on DSP benchmarks. Unroll-and-jam and Loop Unrolling A new method that integrates a communication cost model with an integer-optimization problem is developed to determine unroll amounts for loop unrolling and unroll-and-jam automatically for a specific loop on a specific architecture. These techniques have been implemented and tested using DSP benchmarks on simulated, clustered VLIW architectures and a real clustered, embedded processor, the TI TMS320C64X. The results show that the new techniques achieve an average speedup of 1.72-1.89 on five different clustered architectures. These techniques have been implemented and tested using DSP benchmarks on simulated, clustered VLIW architectures and a real clustered, embedded processor, the TI TMS320C64X. The results show that the new techniques achieve an average speedup of 1.72-1.89 on five different clustered architectures.

Automatically determine the membership function based on the maximum entropy principle

With the growing need of big-data processing in diverse application domains, MapReduce (e.g., Hadoop) has become one of the standard computing paradigms for large-scale computing on a cluster system. Despite its popularity, the current MapReduce framework suffers from inflexibility and inefficiency inherent to its programming model and system architecture. In order to address these problems, we propose Vispark, a novel extension of Spark for GPU-accelerated MapReduce processing on array-based scientific computing and image processing tasks. Vispark provides an easy-to-use, Python-like high-level language syntax and a novel data abstraction for MapReduce programming on a GPU cluster system. Vispark introduces a programming abstraction for accessing neighbor data in the mapper function, which greatly simplifies many image processing tasks using MapReduce by reducing memory footprints and bypassing the reduce stage. Vispark provides socket-based halo communication that synchronizes between data partitions transparently from the users, which is necessary for many scientific computing problems in distributed systems. Vispark also provides domain-specific functions and language supports specifically designed for high-performance computing and image processing applications. We demonstrate the performance of our prototype system on several visual computing tasks, such as image processing, volume rendering, K-means clustering, and heat transfer simulation.

This thesis presents techniques for modeling and control of X-ray image processing tasks, aiming at the fluent execution of a multitude of diagnostic and interventional X-ray imaging applications on a multi-core computing platform. A general trend in medical imaging systems is the execution of image processing on general-purpose programmable platforms, instead of specific dedicated hardware solutions. This even holds for the newest functionality such as image analysis, which performs computations in a more stochastic manner, rather than stream-based processing. The trend of more dynamic image processing and the new analysis functions in X-ray imaging, combined with the desire for more programmable and flexible future systems forms the starting point of our research. The first contribution of this thesis is the modeling and optimization of the processing performance of stream-based medical imaging tasks, in particular image quality enhancement for interventional X-ray. We have defined rules for specifying and dividing image processing tasks for parallel processing, to optimize the related memory communication. Similarly, for the computing architecture, we have specified the detailed timing requirements for data storage and communication, incorporating memory-access times. In the initial situation, the computing system was fully loaded, both in terms of memory and computation, and the latency was strongly time varying and could not be predicted. Our modeling has yielded a good understanding of the actual execution and its critical factors. The model has eventually lead to an approach for task splitting leading to a sharper system optimization with respect to essential parameters, such as latency. However, the method for building the model is time consuming. The same holds for the architecture. Nevertheless, the experiment has been highly valuable since the system optimization is associated with a considerable system cost and the resulting alternative execution architectures have provided ways for cost reduction or adding attractive functionality to the same system, which currently is executed on an additional separate platform. The second contribution of this thesis is the modeling and prediction of the computation time of feature-based medical imaging tasks, where the task complexity is non-deterministic and the resource demands fluctuate with the image content. We have focused in particular on applications for advanced diagnosis with image analysis and motion-compensated subtraction imaging. We demonstrated that the computation time for tasks with purely random resource usage can be successfully predicted with zero-order Markov chains. Furthermore, first-order Markov chains are used if temporal correlation between the computation time statistics exists for only short periods of time. For structural correlations between image frames, scenario-based methods have to be added to the obtained prediction model, extracted from the flow graph of tasks. Alternatively, when the computational complexity depends on external (spatial) factors, the prediction model is based on spatial (look-ahead) prediction. Experimental results have shown that it is possible to predict the computation time of feature-based medical image applications, even if the flow graph dynamically switches between groups of tasks. We have found an average accuracy for two different application scenarios between 95 – 97%, with sporadic excursions of the prediction error up to 20 – 30%. The third contribution of this thesis is the design of a control system for the fluent execution of a set of applications on a multi-core platform, where some of the applications have a fluctuating resource demand and others have strict low-latency requirements. As a possible solution, we have implemented options for scalability in applications for three application scenarios, using task scaling, task skipping and task delaying. A Quality-of-Service (QoS) control system then maintains constant throughput and latency by dynamically switching between application quality modes. A global resource manager maintains the overall resource usage of the system and local application controllers are responsible for resource estimation and quality control of each individual application. The global resource manager is based on a modified version of the Lagrangian relaxation algorithm that searches for suitable combinations of quality levels for a set of concurrent running applications. The research has been validated by executing three medical imaging applications in parallel, from which two are critical in latency. It is interesting to know that the above solution has a high industrial relevance because it can facilitate in reducing system costs for applications that are already released on the market. The work has resulted in a solution featuring a combination of both interventional and diagnostic signal processing, which are executed on a single computing device with nearly the same quality, as compared to two separated computers with those tasks in the original setting. Furthermore, the techniques can be employed for different classes of systems, with different cost-performance points.

Due to the rising complexity of modern embedded media applications (EMAs), the instruction level parallelism (ILP) is not sufficient to meet the need. Compilers must have the capability to exploit the superword level parallelism (SLP), which can expose more concurrency lying in applications, minimize the latency created by memory access and hence produce more efficient codes. The loop is a good candidate for SLP extraction because of its paralleled structure between iterations. This work analyzes the memory access patterns found in EMAs and presents our method of loop unrolling to fully utilize these patterns to generate efficient Single Instruction Multiple Data (SIMD) instructions. Experimental results performed on TriMedia TM-1300 processor for the H.264 encoder show performance improvement by a factor ranging from 3 to 30 times with an average of 12 times.

This paper proposes a superscalar architecture SARCH. An efficient mechanism for exploiting instruction‐level parallelism (ILP) is required to achieve high performance on nonnumerical applications. SARCH employs boosting for speculative execution to exploit large ILP, and a branch scheme to reduce branch penalty. Although these mechanisms are realized by simple hardware, code motion beyond basic blocks by compilers is necessary. A code scheduler is developed which performs global scheduling for the boosting and the delayed branch. The performance evaluation shows that the scheduled code achieves 1.52 time performance improvement over the original code, and 1.75x speed‐up over the scalar processor.

Solving a problem can have multiple methods, each having its own merits and demerits. The ultimate level of complexity of solution models is highly subjective in nature because a method easy for one person may be much difficult for others. Moreover, methods friendly for humans need not be suitable for automated systems like computers. Similar is the case among various automated systems too. All depend on the nature of the problem and the solver, availability of resources, optimization requirements and the like. For example, loops in source code reduce the complexity while programming but give additional overhead during execution. So, optimization of programs by reducing the number of loops can make considerable improvement in performance at runtime. There are several techniques for optimizing the loops. This study is based on the popular loop optimization technique known as Loop unrolling which is having own advantages and disadvantages, but able to open up the additional scope for enhanced parallelism and automated code generation.