An efficient architecture for carry select adder

In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data-processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.

Carry select adder (CSLA) one of the fastest adders used in complex data processing to perform fast arithmetic functions. Minimum amount of power consumption is a major driving force behind the development of CMOS technologies. From the structure of CSLA it is clear that there is scope for reducing the area & power consumption in the CSLA. In this paper 8T full adder is used as a building block for 8-bit SQRT CSLA. 8T full adder is designed by XNOR-XNOR hybrid CMOS design. Based on this modification, 8-, 16-, 32-, 64-bit SQRT CSLA architecture has been developed & compared with the regular SQRT CSLA. Binary to Excess one converter (BEC) based CSLA are analyzed to study the data dependence & to identify all redundant logic operations. In this paper, all the redundant logic operations in the conventional CSLA are eliminated and a new logic formulation where carry select operation is scheduled before the calculation of final sum is proposed. Gate Diffusion Input (GDI) technique of low power digital combinatorial circuit design is also described. The frequency of operation is 5 MHZ. This work estimates the performance of the proposed design with the regular design in terms of area & power through the logic design & layout in 250nm CMOS process technology & implemented using Tanner (S-Edit) tool. The result analysis shows that the proposed structure is better than the conventional CSLA.

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic

In electronic applications, better performance of the digital systems can be achieved using a faster adder circuit. This paper shows a modified carry-select adder (CSA) architecture which has low power and reduced area compared to the regular CSA. This high speed CSA is achieved by replacing the existing binary to excess-1 converter (BEC-1) with D-latch enabled CSA. Regular square-root CSA (SQRT CSA) architectures have also been developed and compared with the proposed BEC-1 D-latch enabled CSA. This work evaluates the performance of delay, area, power, and their products for existing and proposed CSA designs. This shows that proposed D-latch CSA structure is better than the regular and modified SQRT CSA and existing Ripple CSA. The proposed CSA architecture requires approximately 86 % fewer gates and 77 % shorter delay than the original CSA designs.

In this paper, a new carry select adder (CSLA) architecture is proposed with a lower area and a higher speed compared to previous CSLAs. The proposed CSLA is a low-area and high-speed design utilizing a new add-one circuit that is used instead of the second ripple carry adder (RCA) with the input carry equal to one (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> =1) inside each group of the basic CSLA. Moreover, to expedite the add operation, a new grouping structure is proposed instead of the basic square-root (SQRT) grouping as well as utilizing a faster RCA in each group. Despite the fact that the proposed CSLA has not attained the lowest power consumption among all existing designs based on the PDK 45nm standard cell library, but it has achieved the lowest area and delay compared to previous CSLAs. Implementation results show that 8 to 33% area reduction and 12 to 44% speed improvement are achieved in the proposed CSLA compared to previous designs.

In this paper, two-dimensional Discrete Wavelet Transform (2-D DWT) based image compression is presented with the help of developed Enhanced square root carry select adder (ESCSLA). The Enhanced Carry select adder is replacing the RCA and BEC unit to D-latch circuit. It provides better results than compared to the conventional adders. DWT and ESCSLA circuit is designed through Very Large Scale Integration (VLSI) System design environment. Low power consumption, less area and high speed are the main concerns in VLSI System design. Hence, our aim is to reduce the hardware complexity of ESCSLA and improve the performance of DWT in terms VLSI concerns. In our work, three levels of decomposition are made for image compression. With the help of pixel values of image and Enhanced square root carry select adder circuit, 2-D DWT image compression technique is implemented through Verilog HDL design. The performance of ESCSLA circuit is better than conventional Binary to Excess1 (BEC) based Square Root Carry Select Adder (SQRT CSLA) in terms of silicon area and power consumption. Hence, the performance of DWT also increased when incorporating EHRCA circuit into addition process of DWT computation.

In this research work the application of an efficient Carry Select Adder (CSLA) performance and its implementation in the diagnosis of brain tumour with help of convolution theories that improve the quality of the image is concentrated, because of the need for several pairings of RCA to produce the sum of the partial section, the CSLA isn't time efficient. Because of the use of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input, the CSLA is used in several systems to mitigate the issue of carry propagation delay that occurs by generating various carries, and to get the sum select a carry. However, the CSLA isn't time efficient. The main goal of this project is to use a Binary to Excess-1 Converter instead of an RCA in a typical CSLA to achieve maximum speed and low power consumption. The employment of a large number of efficient adders combined with higher image quality could result in a faster and more accurate diagnosis of a brain tumour. Here RCA denotes the Ripple Carry Adder section. During this research, a method of CSLA with D LATCH is implemented in order to reduce facility utilization even more. In the XILINX ISE design suite 14.5 tools, the look of the Updated Efficient Area-Carry Select Adder (UEA-CSLA) is reviewed and intended. By completing the cerebrum tumour discovery, this VLSI arrangement is used in image preparation application. In medicinal pictures estimation, the multi phantom picture isn't much proficient to defeat this disadvantage, therefore the hyper spectral picture method utilized here is presented as a sifting procedure in VLSI innovation restriction of cerebrum tumour, which is performed using Updated Efficient Area-Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, micro processors and digital signal processors etc. A system's performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the whole system and also it is occupying more area consuming. The Carry Select Adder (CSLA) provides a good compromise between cost and performance in carry propagation adder design. A Square Root Carry Select Adder using RCA is introduced but it offers some speed penalty. However, conventional CSLA is still area-consuming due to the dual ripple carry adder structure. In the proposed work, generally in Wallace multiplier the partial products are reduced as soon as possible and the final carry propagation path carry select adder is used. In this paper, modification is done at gate level to reduce area and power consumption. The Modified Square Root Carry Select-Adder (MCSLA) is designed using Common Boolean Logic and then compared with regular CSLA respective architectures, and this MCSLA is implemented in Wallace Tree Multiplier. This work gives the reduced area compared to normal Wallace tree multiplier. Finally an area efficient Wallace tree multiplier is designed using common Boolean logic based square root carry select adder.

The signal processing system is extremely popular in this day and age. All of the primary circuits in the digital signal processing system are built around the adder, which is the fundamental building block. Today’s needs for lowering the delay, space, and power consumption of adder circuits boost the overall efficiency of the system, propelling it to the next stage of technological development. Despite the fact that the Carry Select Adder (CSLA) takes up more space, it is being utilised in place of the ripple carry adder in order to reduce propagation delays. In other models, a Carry Select Adder based on a Binary to Excess-I Converter (BEC) was utilised, which required fewer logic resources than a standard CSLA and was hence more energy efficient. The fact that these CSLAs reject one sum after the calculation, however, means that they are not more efficient. As a result, the delay was not significantly decreased. It is necessary to apply the reduced logic CSLA in order to overcome this challenge. However, by employing the Gate Diffusion Input (GDI) Technique, it is possible to achieve a lower delay than the previously suggested reduced logic CSLA. The suggested technique consumes less power and has a shorter propagation latency than existing techniques. In addition, the number of transistors necessary for the circuit was reduced by implementing this GDI-based CSLA. It is possible to create an efficient adder using this technique, as seen above.

A low-cost high-speed self-checking carry select adder with multiple-fault detection

In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed CSLAs reduced power consumption by 68.4–72.2% with a slight delay increase for different bit widths. As the dual carry adder had much fewer transistors than the two regular full adders, the area of the proposed CSLAs was reduced by 45.8–51.1%. The area-power-delay product of the proposed CSLA improved 5.1×–6.73× compared with the regular CSLA.

Adders are the most important fundamental blocks of the digital systems which are used in a wide variety of applications. Among them the first basic adder is the Ripple Carry Adder (RCA) and the fastest adder is the Carry Select Adder (CSA). Though all these adders are existed, the speed adding using low power and optimized area is still a challenging issue. In this paper a new technique, Modified Gate Diffusion Input (MOD-GDI) is used to achieve an optimized design with less transistor count and low power dissipation. In the proposed work the 8-bit, 16-bit Ripple Carry Adder and the 8-bit, 16-bit Carry Select Adder have been designed using the CMOS and MOD-GDI techniques. The comparison of their power dissipations and overall transistor count is done and proved that low power and optimized designs are achieved through MOD-GDI technique. The simulation is carried out using Mentor Graphics tool with a supply voltage of 1.8 V at 90 nm technology.

The adder is the maximum usually used mathematics block in programs inclusive of &lt;span lang="EN-US"&gt;central processing unit (CPU) and virtual sign processing. As a result, it is important to expand a space-saving, low-strength, high-overall performance adder circuit. The hassle is diagnosed to layout mathematics sub structures with minimized strength dissipation, low area, and minimal time postpone of common-sense circuits. In conventional &lt;a name="_Hlk95894088"&gt;&lt;/a&gt;carry select adder (CSA), the time required to generate the sum output is less than other basic adder circuits but the principal difficulty is the location because the variety of transistors used to put in force the CSA circuit is fairly more. So, the area increases because of which the overall power consumption of the circuit will be more. If it's far viable to lessen the variety of transistors used withinside the structure of CSA adder, then, the strength intake of the circuit may be decreased or even the reaction time will improve. By lowering the area of the adder circuit, the suggested solution intends to reduce power consumption and latency.&lt;/span&gt;

Many processor architectures, such as digital signal processors and microprocessors, rely on arithmetic circuits. The efficient implementation and design of arithmetic units necessitates the creation of binary adder structures in a similar manner. A ripple carry adder has a tiny surface area yet is slower. Carry propagation is also one of the reasons why the total for each bit is generated sequentially after the preceding carry arrives. The primary idea behind this study is to replace the RCA in a normal CSLA with a binary to excess-1 converter (BEC) to achieve high speed, area efficiency, and low power consumption. The following architectures are implemented using Verilog HDL as a programming language, and their simulation results are also shown.KeywordsBinary to excess-1 converters (BEC)Carry select adder (CSLA)