An efficient caching support for critical sections in large-scale shared-memory multiprocessors

Directory-based protocols are currently the method of choice to enforce cache coherence in large-scale shared-memory multiprocessors. The problems associated with these hardware schemes include their lack of scalability, although various suggestions have been made to ameliorate this drawback, and the loss of performance due to false sharing. Software controlled cache coherence (SCCC) is an alternative that solves the scalability problem at the possible expense of a serious loss in performance since many compile-time decisions on cacheability are conservative. The authors perform a comparative study of hardware and software cache coherence based on instruction-level simulations of two benchmarks. The studies do not shy away from realistic SCCC difficulties such as multi-word lines and DOAcross loops. The simplification in hardware and in protocols result in a slight performance loss for SCCC, a loss that becomes relatively smaller and negligible with larger memory latencies. >

Efficiently maintaining cache coherence is a major problem in large-scale shared memory multiprocessors. Hardware directory coherence schemes have very high memory requirements, while software-directed schemes must rely on imprecise compile-time memory disambiguation. Recently proposed dynamically tagged directory schemes allocate pointers to blocks only as they are referenced, which significantly reduces their memory requirements, but they still allocate pointers to blocks that do not need them. The authors present two compiler optimizations that exploit the high-level sharing information available to the compiler to further reduce the size of a tagged directory by allocating pointers only when necessary. Trace-driven simulations are used to show that the performance of this combined hardware-software approach is comparable to other coherence schemes, but with significantly lower memory requirements. In addition, these simulations suggest that this approach is less sensitive to the quality of the memory disambiguation and interprocedural analysis performed by the compiler than software-only coherence schemes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Several mechanisms have been proposed for maintaining cache coherence in large-scale shared memory multiprocessors. Two important factors that distinguish these coherence mechanisms are: 1) the coherence enforcement strategy, such as updating or invalidating, that is used to prevent access to stale data; and 2) the coherence detection strategy, which is used to detect the existence of incoherent cached copies either at compile-time or at run-time. This paper examines the range of performance that can be realized by a compiler-directed coherence mechanism using three different levels of compiler ability. This performance is compared to the performance of the updating and the invalidating directory schemes. In addition, the performance of all three coherence schemes is compared with respect to different cache block sizes.

Cache coherence enforcement and memory latency reduction and hiding are very important and challenging problems in the design of large-scale distributed shared-memory (DSM) multiprocessors. We propose an integrated framework to solve these problems through a compiler-directed cache coherence scheme called the Cache Coherence with Data Prefetching (CCDP) scheme. The CCDP scheme enforces cache coherence by prefetching the potentially stale references in a parallel program. It also prefetches the nonstale references to hide their memory latencies. To optimize the performance of the CCDP scheme, some prefetch hardware support is provided to efficiently handle these two forms of data prefetching operations. We also developed the compiler techniques utilized by the CCDP scheme for stale reference detection, prefetch target analysis and prefetch scheduling. We evaluated the performance of the CCDP scheme via execution-driven simulations of several applications from the SPEC CFP95 and the Perfect benchmark suites. The simulation results show that the CCDP scheme provides significant performance improvements for the applications studied.

DOALL loops are tiled to exploit DOALL parallelism and data locality on GPUs. In contrast, due to loop-carried dependences, DOACROSS loops must be skewed first in order to make tiling legal and exploit wavefront parallelism across the tiles and within a tile. Thus, tile size selection, which is performance-critical, becomes more complex for DOACROSS loops than DOALL loops on GPUs. This paper presents a model-driven approach to automating this process. Validation using 1D, 2D and 3D SOR solvers shows that our framework can find the tile sizes for these representative DOACROSS loops to achieve performances close to the best observed for a range of problem sizes tested.KeywordsExecution TimeLoop NestThread BlockTile SizeActual Execution TimeThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The problem of cache coherence in large-scale shared-memory multiprocessors has been addressed using directory-schemes. Two problems arise when the number of processors increases: the network latency increases and the implementation cost must be kept acceptable. The authors present a tree-based cache coherence protocol called the scalable tree protocol (STP). They show that it can be implemented at a reasonable implementation cost and that the write latency is logarithmic to the size of the sharing set. How to maintain an optimal tree structure and how to handle replacements efficiently are critical issues the authors address for this type of protocol. They compare the performance of the STP with that of the scalable coherent interface (SCI) (IEEE standard P1596) by considering a classical matrix-oriented algorithm targeted for large-scale parallel processing. They show that the STP manages to reduce the execution time considerably by reducing the write latency. >

Latency and synchronization overheads have been identified as two fundamental problems in large-scale shared memory multiprocessors. The notion of partial sharing of variables is introduced, and architectures based on hierarchical memories which exploit this notion of partial sharing to reduce the latency and synchronization overheads significantly are suggested. A particular class of architectures, the tree structure, hierarchical memory multiprocessor architectures (THMMs), is examined by suggesting an implementation and considering the execution and the performance of several well-known applications such as matrix multiplication, solution of partial differential equations, solution of linear recurrence relations, barrier synchronization, and reduction operations. Speedup and cost figures for these examples are compared when executing on the THMM and on a conventional memory multiprocessor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Dynamiically tagged directories have been recently proposed as a memory-efficient mechanism for maintaining cache coherence in large-scale shared-memory multiprocessors. In order to efficiently use these directories, the number of pointer operations must be minimized and pointers should be allocated as late as possible. If pointers are allocated too early, frequent pointer overflow will occur, which in turn may cause cache thrashing.

Appropriate solution of the well-known cache coherence problem in shared memory multiprocessors is one of the key issues in improving the performance and scalability of these systems. Hardware methods are convenient because of their transparency for software. They also offer good performance since they deal with the problem dynamically. Hardware cache coherence schemes can be principally divided into two large groups: directory and snoopy protocols. This survey underlines their principles and summarizes a relatively large number of relevant representatives from both groups. The coherence problem in multilevel caches is also briefly considered. Special attention is devoted to cache coherence maintenance in large scalable shared memory multiprocessors. >

Operating systems for most current shared-memory multiprocessors must maintain translation lookaside buffer (TLB) consistency across processors. A processor that changes a shared page table must flush outdated mapping information from its own TLB, and it must force the other processors using the page table to do so as well. Published algorithms for maintaining TLB consistency on some popular commercial multiprocessors incur excessively high synchronization costs. We present an efficient TLB consistency algorithm that can be implemented on multiprocessors that include a small set of reasonable architectural features. This algorithm has been incorporated in a version of the MACH operating system developed for the IBM Research Parallel Processor Prototype (RP3).

This paper studies the interaction between the access protocol used to provide arbitration for a wavelength-division multiple access photonic network and the cache coherence protocol required to support a distributed shared memory environment. The architecture is based on wavelength division multiplexing which enables multiple multi-access channels to be realized on a single optical fiber. Larger blocks are supported to reduce the per bit overhead and increase the exploitation of spatial locality, while false sharing is reduced through a mechanism to provide a finer granularity of invalidation. Two main approaches have been considered to harness the enormous available bandwidth of WDMA optical networks: reservation (control-channel based) or pre-allocation media access protocols. This paper extends the function of a control channel to include broadcast support of cache-level control information, in addition to its primary role of data channel reservation, thereby enabling a snooping based coherence protocol to be considered. Larger snooping-based multiprocessors may be possible with this approach. Two major scenarios are considered through trace-based discrete-event simulation in this paper: a system with a directory based cache coherence protocol and a pre-allocation based WDMA access protocol is compared to a system with a snooping based cache coherence protocol and a reservation based WDMA access protocol. >

Cache Coherence in Multiprocessors: A Survey

The main function of parallelizing compilers is to analyze sequential programs, in particular the loop structure, to detect hidden parallelism and automatically restructure sequential programs into parallel subtasks that are executed on a multiprocessor. This article describes the design and implementation of an efficient parallelizing compiler to parallelize loops and achieve high speedup rates on multiprocessor systems. It is well known that the execution efficiency of a loop can be enhanced if the loop is executed in parallel or partially parallel, such as in a DOALL or DOACROSS loop. This article also reviews a practical parallel loop detector (PPD) that is implemented in our PFPC on finding the parallelism in loops. The PPD can extract the potential DOALL and DOACROSS loops in a program by verifying array subscripts. In addition, a new model by using knowledge‐based approach is proposed to exploit more loop parallelisms in this paper. The knowledge‐based approach integrates existing loop transformations and loop scheduling algorithms to make good use of their ability to extract loop parallelisms. Two rule‐based systems, called the KPLT and IPLS, are then developed using repertory grid analysis and attribute‐ordering tables respectively, to construct the knowledge bases. These systems can choose an appropriate transform and loop schedule, and then apply the resulting methods to perform loop parallelization and obtain a high speedup rate. For example, the IPLS system can choose an appropriate loop schedule for running on multiprocessor systems. Finally, a runtime technique based on the inspector/executor scheme is proposed in this article for finding available parallelism on loops. Our inspector can determine the wavefronts of a loop with any complex indirected array‐indexing pattern by building a DEF‐USE table. The inspector is fully parallel without any synchronization. Experimental results show that the new method can resolve any complex data dependence patterns where no previous research can. One of the ultimate goals is to construct a high‐performance and portable FORTRAN parallelizing compiler on shared‐memory multiprocessors. We believe that our research may provide more insight into the development of a high‐performance parallelizing compiler. Copyright © 2001 John Wiley &amp; Sons, Ltd.

Shared-memory multiprocessors are known to have intrinsic overheads imposed by synchronization and data coherency. Release consistency is a memory consistency model, which alleviates these overheads by relaxing the execution order of a parallel program. This paper proposes techniques to improve the performance of release consistency by combining and QOLB synchronization with write caches. In our scheme, writes in a critical section are deferred with a write cache until a lock variable protecting the critical section is released. On a release, the deferred writes are performed not globally but only to a processor that will execute the critical section exclusively at the next time. To determine the next processor at the execution time, we adopt QOLB primitives as synchronization primitives. We evaluate the performance of our scheme by program driven simulation. Experimental results show that it can improve the performance of shared-memory multiprocessors by reducing read stall time and synchronization stall time.

Time/Contention Trade-Offs for Multiprocessor Synchronization