An efficient hardware realization of diamond search algorithm for motion estimation task in video compression applications

In this paper, a modified diamond search (MDS) algorithm is proposed for fast motion estimation based on the well known diamond search (DS) algorithm. A set of computationally efficient algorithms that can be applied to any block matching algorithm and is applied to the DS as a study case achieves higher complexity reduction than DS algorithm without further relative PSNR (peak signal to noise ratio) degradation compared to full search (FS). First, dynamic internal stop search (DISS) algorithm is used to reduce the internal redundant SAD (sum of absolute difference) operations between the current and the candidate blocks using an accurate dynamic threshold. Second, a dynamic external stop search (DESS) greatly reduces the unnecessary operations by skipping all the irrelevant blocks in the search area. In addition, early search termination and adaptive pattern selections techniques are applied to the proposed MDS as initialization steps to achieve even higher complexity reduction. The accuracy of the proposed model threshold equations guarantee not to fall into a local minima. Experiments show that the proposed MDS algorithm reduces the computations greatly up to 99% and 20% compared with the conventional FS algorithm and DS respectively with no significant degradation in both the PSNR and the bit-rate.

A Fast Diamond Search (FDS) algorithm based on the conventional Diamond Search (DS) algorithm is proposed. Two computationally efficient algorithms are applied to the conventional DS in order to reduce the computations with an acceptable degradation in the coding efficiency. The first algorithm is the Internal Stop Search (ISS) that is used to reduce the internal redundant SAD (Sum of Absolute Difference) operations between both the current and the reference blocks. The second algorithm is the External Stop Search (ESS) that is used to skip the unnecessary operations by skipping all the irrelevant blocks in the search area. Both of these algorithms use adaptive models that accurately remove the unnecessary operations considering small degradation in the coding efficiency. In addition, early search termination and adaptive pattern selections techniques are applied to the proposed FDS as initialization steps to achieve even higher complexity reduction. Experiments show that the proposed FDS algorithm reduces the computations greatly up to 99% and 20% compared to the conventional FS algorithm and DS respectively.

A novel fast integer-pixel multi-pattern search algorithm is proposed in this paper. The cross search pattern (CSP) is used to get the coarse position of the best matching point, then small diamond search pattern (SDSP) or small square search pattern (SSSP) is chosen to locate the best matching point accurately according to the size of the partitioned block. In order to reduce the number of search points, the judging threshold is applied, which is determined by the compensation value and the sum of absolute difference (SAD) values of three adjacent blocks. Experimental results show that, compared to Unsymmetrical cross multi-hexagon grid search algorithm (UMHSA) and diamond search algorithm (DSA), the proposed algorithm reduces search time greatly, and keeps the generated bytes and the PSNR of luminance signals in similar levels.

The full search block-matching algorithm is the simplest, but computationally very intensive approach. In recent years there was substantial progress in block motion estimation algorithms. Important milestones on this path were such algorithms as two-dimensional logarithmic search, three-step search, four step search, and diamond search. All these methods try to minimize the amount of search points applying sum of absolute differences (SAD) or equivalent metrics for each point. There were some works that studied partial SAD (PSAD) but mostly concentrated on a constant decimation factor. What we tried to study in this work is the performance of one of the best block matching search algorithms in combination with adaptive PSAD as a matching metric. The idea is that we use original motion estimation based on spatio-temporal correlation method, but instead of using SAD as a matching metric we use PSAD with adaptively chosen decimation factor. Our simulation results show that for high motion sequences PSNR degradation between full search and the proposed method was around 0.1-0.7 dB. The computational complexity reduction of 650-1700 times (compared with the full search) and 9 times (compared to the original method) is pretty big and may be well worth this video quality decrease. In the case of more static sequences PSNR degradation between full search and the original motion estimation method was around 0 dB. When we compare the original method with the proposed one the degradation increases to 0.1 dB. The computational complexity reduction was around 1600-1700 times (compared with the full search) and 5-7 times (compared to the original method).

This paper presents an efficient architecture for Motion Estimation (ME) based on the Diamond Search (DS) Algorithm. This architecture also includes the Motion Compensation (MC) for luminance samples, reusing internal ME results and avoiding the additional external memory accesses for the MC operation. The proposed architecture also generates inputs for a Fractional Motion Estimation (FME) for quarter sample precision, as proposed by the H.264/AVC standard. The main goal of this work is to design a low cost ME architecture for the DS algorithm with reduced number of external memory accesses and ready to be integrated with a fractional interpolator. The designed architecture was synthesized to Altera Stratix 4 family of FPGAs and in the worst case scenario, this architecture is able to process Full HD (1080p) videos in real time.

SAD(Sum of Absolute Difference) 알고리즘은 동영상 인코더에서 가장 많은 시간이 소용되는 것으로 잘 알려진 움직임 추정에서 가장 자주 계산이 수행되는 알고리즘으로, 동영상 인코딩 수행시간을 줄이기 위해서 우선적으로 최적화 구현되어야 하는 알고리즘이다. 본 논문에서는 VLIW 기반 고성능 DSP 프로세서에서의 조건 분기를 갖는 SAD 알고리즘의 최적 스케줄링 구현 방법을 제안한다. 제안 방법은 먼저 조건 분기를 갖는 중첩 루프를 VLIW 구조가 제공하는 ILP(Instruction Level Parallelism) 능력을 잘 활용할 수 있도록 충분한 크기의 루프 몸체를 가지며 또한 빨리 루프를 탈출 할 수 있는 조건 분기를 갖는 단일 루프로 변환한 후에, 모듈로 스케줄링 기법을 적용하여 VLIW 기반 프로세서에서 최적화 스케줄링 구현을 한다. 제안된 구현 방안을 TMS320C6713에서 구현하고, 코드 크기 및 수행 시간에 대한 성능 분석을 하였다. 구현된 최적화 SAD 루틴은 코드 크기도 크지 않아 임베디드 응용에 적합하며, 이 SAD 구현을 사용한 H.263 인코더가 그렇지 않은 H.263 인코더보다 훨씬 좋은 성능을 보임을 실험을 통해 확인하였다. SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

In block motion estimation, a search pattern with a different shape or size has a very important impact on search speed and distortion performance. A square-shaped search pattern is adopted in many popular fast algorithms. Recently, a diamond-shaped search pattern was introduced in fast block motion estimation and has exhibited a faster search speed. Based on an in-depth examination of the influence of the search pattern on speed performance, we propose a novel algorithm using a hexagon-based search pattern to achieve further improvement. The hexagon-based search pattern is investigated in comparison with diamond search pattern and demonstrates significant speedup gain over the diamond-based search. Analysis shows that a speed improvement rate of the hexagon-based search (HEXBS) algorithm over the diamond search (DS) algorithm can be over 80% for locating some motion vectors in certain scenarios. In short, the proposed HEXBS algorithm can find the same motion vector with fewer search points than the DS algorithm. Generally speaking, the larger the motion vector, the more search points the. HEXBS algorithm can save, which is further justified by experimental results.

This paper presents the architectural design for Motion Estimation (ME) based on the new Multi-Point Diamond Search block matching algorithm. This algorithm reduces the local minima falls in the ME search process, increasing the quality of the ME prediction results. This paper presents a software evaluation about the MPDS which presented an average PSNR gain of 3.57dB and a maximum PSNR gain of 7.86dB when compared with the Diamond Search algorithm. The designed architecture was synthesized to an Altera Stratix 4 FPGA and, in the worst case scenario, this architecture is able to process HDTV 720p videos in real time at 28 frames per second.

The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity in the video encoder. This high consumption of the computational resources puts a limit on the performance of encoders, especially for full HD or ultra HD videos, in terms of coding speed, bit-rate and video quality. Thus the major part of this work concentrates on the computational complexity reduction and improvement of timing performance of motion estimation algorithms for HEVC standard. First, a new strategy to calculate the SAD (Sum of Absolute Difference) for motion estimation is designed based on the statistics on property of pixel data of video sequences. This statistics demonstrates the size relationship between the sum of two sets of pixels has a determined connection with the distribution of the size relationship between individual pixels from the two sets. Taking the advantage of this observation, only a small proportion of pixels is necessary to be involved in the SAD calculation. Simulations show that the amount of computations required in the full search algorithm is reduced by about 58% on average and up to 70% in the best case. Secondly, from the scope of parallelization an enhanced TZ search for HEVC is proposed using novel schemes of multiple MVPs (motion vector predictor) and shared MVP. Specifically, resorting to multiple MVPs the initial search process is performed in parallel at multiple search centers, and the ME processing engine for PUs within one CU are parallelized based on the MVP sharing scheme on CU (coding unit) level. Moreover, the SAD module for ME engine is also parallelly implemented for PU size of 32×32. Experiments indicate it achieves an appreciable improvement on the throughput and coding efficiency of the HEVC video encoder. In addition, the other part of this thesis is contributed to the VLSI architecture design for finding the first W maximum/minimum values targeting towards high speed and low hardware cost. The architecture based on the novel bit-wise AND scheme has only half of the area of the best reference solution and its critical path delay is comparable with other implementations. While the FPCG (full parallel comparison grid) architecture, which utilizes the optimized comparator-based structure, achieves 3.6 times faster on average on the speed and even 5.2 times faster at best comparing with the reference architectures. Finally the architecture using the partial sorting strategy reaches a good balance on the timing performance and area, which has a slightly lower or comparable speed with FPCG architecture and a acceptable hardware cost

An enhanced constrained one-bit transform (C1BT)-based fast motion estimation (ME) method is proposed. Binary transform-based ME identifies the proper motion vector by transforming the 8-bit pixels in the original image into a low bit depth of the bit plane, substantially reducing the computational complexity and facilitating hardware implementation by using the number of non-matching points (NNMPs) instead of the sum of absolute difference (SAD). However, a motion block size is N × N , therefore the dynamic range of NNMP (0 ≤ NNMP ≤ N × N ) is decreased to 1/256 compared to that of the SAD with 8-bit images (0 ≤ SAD ≤ 256 × N × N ). The higher the NNMP between the current bit plane and the previous bit plane, the more probable that it will be the block most similar to each other. Therefore, the matching error criterion of NNMP is extended to improve ME performance. Experimental results show that the proposed algorithm improves the performance of ME accuracy by 0.27, 0.38 and 0.67 dB compared to the C1BT-based ME, two-bit transform (2BT)-based ME and 1BT-based ME, respectively.

To decrease the encoding time and to improve the encoding efficiency in a H264 coding converter, this paper presents a parallel small diamond motion estimation search algorithm based on H264. It's based on a new small diamond search and redefined two different search points to start with. Process with small diamond search by parallel, and the better one would be the best matching point. This kind of searching algorithm has almost the same fast rate of Diamond Search algorithm, and reduces the possibility of falling into the partial best. It can realize higher encoding efficiency.

The sum of absolute difference (SAD) is generally adopted as a cost function in motion estimation (ME) and temporal error concealment (TEC) algorithm owing to its efficiency. The hardware architecture of SAD also consumes considerable power dissipation in video codec chip. Hence, the switching-activity analysis on SAD is quite essential from algorithm/architecture perspectives. This work develops the estimation formulas for switching-activity dedicated for SAD engine according to probability theory. The experiment results reveal that the probability error rate (PER) of the SAD engine is as minor as 5.61%. Consequently, this leads to a precise switching-activity estimation of the SAD-based algorithm/architecture for video signal processing.

Motion estimation is the power-hungry block in the video compression system. The sum of absolute difference (SAD) is the most repeated operation in block matching algorithms of the motion estimation subsystem. This paper identifies low-power full adder that is used in the proposed SAD architecture. The proposed SAD method consumes low power as compared to the existing SAD architectures. The designs are implemented using ASIC flow (synthesis) using the Cadence tools and the simulations are done using the Modelsim simulation tools. The synthesis is done using TSMC 180 nm and 45 nm technology libraries; the synthesis is mainly focused on the power consumed, area acquired and latency. This paper implements 4 × 4 (16 input samples) SAD algorithm, and the proposed architecture shows 26.3 % improvement in leakage power, 67.58 % improvement in dynamic power, and 65.6 % improvement in the total power with the 180 nm technology and 13.9 % improvement in the leakage power, 62 % improvement in the dynamic power, and overall 60 % improvement of total power with the 45 nm technology, as compared to the existing architecture.

This paper describes a motion estimation (ME) engine that achieves both power efficiency and coding quality for real-time ultra-high definition video encoders. Sum of absolute difference (SAD) calculations are performed with bit-shortened SAD engines to reduce power, and bit extraction positions are adaptively shifted in accordance with the flatness of picture luminance values to maintain calculation precision. Power simulations with a High Efficiency Video Coding encoder LSI design [2] show that the ME engine reduces power consumption by 18–39% with 4-bit shortened SAD calculation, while coding efficiency loss is suppressed by up to 57% with adaptive bit-shifting. The ME engine is especially effective for high dynamic range pictures with downscaled luminance values, which are suitable for today's 4K and 8K video contents.

In modern video coders, motion is estimated using an algorithm that calculates the distance and direction of motion on a block-by-block basis. In this paper, a new motion estimation scheme is proposed. This scheme uses the sum of absolute difference between the Walsh-Hadamard projections of two blocks as measurement. And integral image is used to perform the scheme. Different from other methodologies using WH projections, the method proposed in this paper does not require iteration over every position to effectively calculate the WH projections of a block at any location. And the complexity of this scheme is regardless of the size (2N×2N) of the block. Comparing to the methods (Full Search, Three Step Search and Diamond Search) based on sum of absolute differences (SAD), experiments show that the proposed scheme significantly reduces computational complexity with little increase in the bit-rate.