An efficient reformulation based architecture for adaptive forward error correction decoding in wireless applications

This paper introduces Adaptive and Reliable Forward Error Correction (AR_FEC), a novel mechanism that is designed to ensure reliable and efficient real-time video delivery for Unmanned Aerial Vehicles (UAVs). UAVs communicate using wireless channels that are inherently unreliable. AR_FEC is an application-layer solution that is inspired by edge computing. It incorporates several elements, specifically, adaptive Forward Error Correction (FEC), dynamic video quality, and Unequal Error Protection (UEP). AR_FEC dynamically adjusts the number of redundancy frames per video Group of Picture (GoP) based on packet loss rate, recent average round-trip times, and cross-layer information such as bandwidth usage and network traffic load. Moreover, AR_FEC reacts to congestion via a dynamic video quality algorithm. By adaptively determining suitable redundancy for the video I-frames and adjusting video quality, significant improvements are achieved. Comprehensive simulations demonstrate that the proposed AR_FEC protocol offers excellent performance for the number of delivered frames, latency, throughput, and delivery of frames, within the delay constraints for real-time multimedia streaming from UAVs.

Optimizing Time-Series forecasting using stacked deep learning framework with enhanced adaptive moment estimation and error correction

Robust image steganography against lossy JPEG compression based on embedding domain selection and adaptive error correction

Studying phase error is central to synthetic aperture radar (SAR) research. Phase error due to the real motion status of the SAR platform and propagation effects can reduce the utility of high-resolution SAR images even with theoretical estimation-based phase error correction. Adaptive optics (AO) can be used to correct optical aberrations. This study proposes an advanced, high-resolution SAR optoelectronic processor by integrating conventional processors with sensor-less AO techniques. This processor provides accurate adaptive phase error correction capabilities. The processing results of SAR echo data demonstrate the effectiveness of the proposed system in adaptive phase error correction and imaging improvement.

To achieve adaptive prediction and error correction of tobacco moisture content after rotary drying in cigarette production, hierarchical cluster analysis was employed to prune the drying parameters of cut tobacco. Leveraging the data characteristics observed during the drying process, we constructed a multivariate linear regression model and a transfer function model based on principal component analysis. For seamless implementation in a computer program, both forecasting models were discretized. The prediction error was corrected online using the moving average method and the second-order exponential smoothing method to enhance the models’ adaptive capability and prediction accuracy. Results from the production environment indicate that while the multivariate linear regression model can generally capture the overall trend of data changes, it falls short in accurately predicting local and real-time moisture variations. In contrast, the transfer function model, enhanced with second-order exponential smoothing, improved the root mean square error (RMSE) and the coefficient of determination (R2) to 0.052 and 0.779, respectively. This adaptive approach effectively accommodates the dynamic characteristics of the rotary drying process, captures random fluctuations in moisture, and delivers precise moisture predictions.

In this paper, an encoder and decoder system is proposed using Bose-Chaudhuri-Hocquenghem (BCH) double-error-correcting and triple-error detecting (DEC-TED) with emerging memories of low power and high decoding efficiency. An adaptive error correction technique and an invalid transition inhibition technique is enforced to the decoder. This is to improve the decoding efficiency and reduce the power consumption and delay. The adaptive error correction gives high decoding efficiency and invalid transition technique reduce the power consumption issue in conventional BCH decoders. The DEC-TED BCH decoder combines these two techniques by using a specific Error Correcting Code Clock and Flip Flops. This technique provides an error correcting encoder and decoder solution for low power and high-performance application using emerging memories. The design simulated in Xilinx FPGA using ISE Design Suite 14.5.

A hybrid forecasting model of carbon emissions with optimized VMD and error correction

New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit environmental requirements. The authors present a reformulation based VLSI architecture for threshold selection for adaptive Viterbi decoding in wireless applications. Through reformulation of the adaptive Viterbi algorithm, the compare operation for threshold selection in the add compare select (ACS) unit is simplified from variable based to constant based and the width of the path metric is reduced. The reformulated architecture results in a significant reduction of hardware complexity in both standard cell and look up table (LUT) technologies. The paper describes the reformulation technique, its VLSI architecture for adaptive Viterbi decoding and its implementations in both ASIC and FPGA technologies. We also demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric memory unit (PMU).

Adaptive error correction in Orthogonal Latin Square Codes for low-power, resilient on-chip interconnection network

Ultra-wideband (UWB) positioning performance is highly related to the accuracy of the coordinates of the fixed anchor nodes, which form the system infrastructure. The process of determining the position of the anchors is called calibration. In an anchor-based system, it is crucial for the fixed nodes to know their locations with the highest possible accuracy. However, in certain situations, it is almost impossible to perform the calibration manually, e.g., during emergency interventions. Moreover, calibration is always delicate and time-consuming. We designed an effortless and accurate self-calibration algorithm that does not require any manual intervention to precisely pinpoint the position of the anchors. This paper presents an innovative algorithm that combines machine learning and exploits the time resolution capabilities of UWB with adaptive physical settings to enable the automatic calibration of the fixed anchor nodes, even in realistic NLOS (non-line-of-sight) conditions. The self-calibration algorithm combines iterative gradient descent to pinpoint the positions of the anchors and uses error detection and correction from a convolutional neural network. Moreover, the algorithm can use a different set of settings for each anchor pair. This is done to ensure the most robust and accurate communication between nodes. Extensive measurements were carried out to allow anchors to estimate distances among each others. Distances were then combined and processed by the self-calibration algorithm. Experimental evaluation in two complex and large environments with many obstacles and reflections shows that accuracy reached by the algorithm is about 2.4 cm on average and 95th percentile is 5.7 cm, in best case. The results refer to the relative positions among the anchors. Results prove that in order to precisely calibrate the anchors nodes in an UWB positioning system, high correctness can be obtained by combining the accuracy of UWB together with deep learning and adaptive PHY modulation schemes.

The combination of linear and nonlinear methods is widely used in the prediction of time series data. This paper analyzes track irregularity time series data by using gray incidence degree models and methods of data transformation, trying to find the connotative relationship between the time series data. In this paper, GM (1,1) is based on first‐order, single variable linear differential equations; after an adaptive improvement and error correction, it is used to predict the long‐term changing trend of track irregularity at a fixed measuring point; the stochastic linear AR, Kalman filtering model, and artificial neural network model are applied to predict the short‐term changing trend of track irregularity at unit section. Both long‐term and short‐term changes prove that the model is effective and can achieve the expected accuracy.

This research, which considered context-sensitive spelling error correction as the classification problem of words along with the context as the solution of semantic ambiguity, has a limitation that correction can be corrected in a particular words pair. To overcome this, this research suggested a technique for detecting and correcting context-sensitive spelling error probabilistically, by selecting the whole eojeol1 as the target words and generating corresponding available candidate. The context-sensitive spelling error correction model suggested by this research is a model based on the noisy channel. It utilized eojeol n-gram model as a language model, and the context-sensitive spelling error rate, the channel probability, was utilized as an equipment for user adaptive context-sensitive spelling error detection and correction. This research composed an evaluation data by transforming eojeol per sentence from 2,000 correct sentences randomly extracted from Sejong corpus to error eojeol. The test result showed function, i.e. precision over 95%, and recall over 70%. This showed the detection and correction method suggested by this research could be applied in the extremely unpredictable error generating language environments.

In this paper we present a method for registering a pair of differently exposed Low Dynamic Range (LDR) images for the purpose of rendering a High Dynamic Range (HDR) image. In general, the images are captured from a moving camera and/or contain moving objects. Therefore, proper registration is required to enable HDR rendering. However, even for equally exposed images, registration is an ill posed problem where errors are expected for a wide range of image pairs. The problem only becomes more challenging for a pair of differently exposed images. We propose an adaptive registration error detection and correction method to address this issue. By combining Optical Flow with the proposed correction method, we achieve state-of-the art results as shown in numerous experiments. The proposed method is simple and has low-complexity, hence allowing for an easy and efficient implementation.

This study presents an improved convergent distributed arithmetic (DA)‐based low complexity pipelined least‐mean‐square filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step‐sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA‐based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bit‐level coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low‐cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time‐window corresponding to the maximum correlation of delayed error signals with a pre‐defined window with n being time instant and . Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th‐order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip‐area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area‐delay‐product and 4.76% less energy‐per‐sample for 64th order with the fourth‐order base unit over the best existing scheme.

Advances in nanoelectronic fabrication have enabled integrated circuits to operate at a high frequency. The finite impulse response (FIR) filter needs only to meet real-time demand. Accordingly, increasing the FIR architecture's folding number can compensate the high-frequency operation and reduce the hardware complexity, while continuing to allow applications to operate in real time. In this work, the folding scheme with integrating input-data and tap folding is proposed to develop a hardware-efficient programmable FIR architecture. With the use of the radix-4 Booth algorithm, the 2-bit input subdata approach replaces the conventional 3-bit input subdata approach to reduce the number of latches required to store input subdata in the proposed FIR architecture. Additionally, the tree accumulation approach with simplified carry-in bit processing is developed to minimize the hardware complexity of the accumulation path. With folding in input data and taps, and reduction in hardware complexity of the input subdata latches and accumulation path, the proposed FIR architecture is demonstrated to have a low hardware complexity. By using the TSMC 0.18 µm CMOS technology, the proposed FIR processor with 10-bit input data and filter coefficient enables a 128-tap FIR filter to be performed, which takes an area of 0.45mm2, and yields a throughput rate of 20M samples per second at 200 MHz. As compared to the conventional FIR processors, the proposed programmable FIR processor not only meets the throughput-rate demand but also has the lowest area occupied per tap.