An Efficient Sorting Algorithm for Non-Volatile Memory

There are many researches and developments on byte accessible non-volatile memory (NVM). Byte accessible NVM can be used as not only storage but also main memory. Non-volatile main memory has two significant merits: reducing power consumption of main memory, flexible system standby and fast resume. However, NVM has bottlenecks in writing and limitation on the number of writing. To overcome this problem, there are some researches on hybrid memory architectures, which combine NVM and DRAM. On hybrid memory architectures, it needs to collect program characteristics of write access and allocate DRAM or NVM based on that characteristics. Previous works proposed to collect and allocate at hardware level or operating system level. At hardware or OS level, memory allocators can collect writing information of wide range of processes. However, they do not know contents of written data, thus they cannot allocate memory based on data characteristics. To solve this problem, we propose a method to obtain characteristics of writing and assign DRAM or NVM based on that information in previous work. The method applies write barrier of language runtimes to collect writing characteristics. This paper describes modification of our previous work and preliminary analysis for implementation the method on Jikes RVM.

Non-volatile Memory (NVM) offers the opportunity to build large, durable B+ trees with markedly higher performance and faster post-crash recovery than is possible with traditional disk- or flash-based persistence. Unfortunately, cache flush and fence instructions, required for crash consistency and failure atomicity on many machines, introduce substantial overhead not present in non-persistent trees, and force additional NVM reads and writes. The overhead is particularly pronounced in workloads that benefit from cache reuse due to good temporal locality or small working sets---traits commonly observed in real-world applications. In this paper, we propose a buffered durable B+ tree (BD+Tree) that improves performance and reduces NVM traffic via relaxed persistence. Execution of a BD+Tree is divided into epochs of a few milliseconds each; if a crash occurs in epoch e, the tree recovers to its state as of the end of epoch e -2. (The persistence boundary can always be made current with an explicit sync operation, which quickly advances the epoch by 2.) NVM writes within an epoch are aggregated for delayed persistence, thereby increasing cache reuse and reducing traffic to NVM. In comparison to state-of-the-art persistent B+ trees, our micro-benchmark experiments show that BD+Tree can improve throughput by up to 2.4x and reduce NVM writes by up to 90% when working sets are small or workloads exhibit strong temporal locality. On real-world workloads that benefit from cache reuse, BD+Tree realizes throughput improvements of 1.1--2.4x and up to a 99% decrease in NVM writes. Even on uniform workloads, with working sets that significantly exceed cache capacity, BD+Tree still improves throughput by 1--1.3x. The performance advantage of BD+Tree increases with larger caches, suggesting ongoing benefits as CPUs evolve toward gigabyte cache capacities.

Non-volatile memories (NVMs) show great potential in replacing DRAM as the main memory in many embedded systems because of their attractive characteristics such as low cost, high density, and low energy consumption. However, the problem of asymmetric read and write costs has to be addressed before the advantages of NVM can be fully exploited. That is, the cost of write operation is much more expensive than the cost of read operation on NVMs. The existing techniques for loop optimization cannot be used effectively with non-volatile main memory because this special feature is not considered. In this paper, we propose an efficient loop scheduling algorithm, the Rotation with Maximum Bipartite Matching (RMBM) algorithm, to address the problem of expensive write operations on non-volatile main memory for chip multiprocessors (CMPs). It achieves high parallelism for a loop and, at the same time, reduces the number of write operations on NVM. The experimental results show that the RMBM algorithm reduces the number of write activities on NVM by 34.5 % on average compared with the traditional rotation scheduling algorithm. The execution time is reduced by 20.5 %, and the energy consumption is also reduced by 15.03 % on average using the RMBM algorithm. In other words, the average lifetime of NVM can be extended by more than 2 times using the proposed technique.

The Sorting Algorithm proposed by C.A.R Hoare  in 1961 by name Quick sort,  which is popularly known for being the fastest sorting algorithm. Quick sort  is still being practiced in the field of computers systems and its applications. The Algorithm whose efficiency to sort random data set is represented in asymptotic notation as  O(n log2 n) and when quick sort algorithm has a input data set which is already Ordered then it takes  a quadratic execution time which is considered as a worst case performance and this behavior is represented in asymptotic notation as O(n2). The  worst case performance is due the scan over heads which occur over the pre-sorted data set, in other words the partitioning gets skewed due to recursive calls and hence results in a quadratic complexity. This research paper presents an algorithm  which minimizes a worst case execution time making it linear when the input list is in non-decreasing order. The paper describes how the improvements are accommodated in the existing quick sort. A priori analysis of  proposed algorithm for different cases is made along with a proof of  correctness. Later the algorithm is verified for its correctness and asymptotic performance. The algorithm is implemented using C++ and also we have compared with other popular quick-sort version.

Hybrid cache architectures (HCAs) containing both SRAM and non-volatile memory (NVM) have been proposed to overcome the disadvantages of NVM-based cache architecture. Most previous works have concentrated on managing write-intensive blocks by storing these blocks to SRAM to reduce the number of the write operations to NVM. However, they have not focused on reducing linefill operations which also occupy a large portion of overall NVM write counts in chip-multiprocessor (CMP) environments. This paper proposes an NVM way allocation scheme, taking into account the NVM linefill counts as well as cache miss rate and the NVM write hit counts during victim selection. Three metrics are introduced to estimate the effectiveness of NVM way allocation: Miss counts change (ΔM), write counts change (ΔW), and NVM write counts change (ΔNVMW). An algorithm to minimize the write counts of NVM based on these metrics is proposed as well. Our experimental results show that dynamic energy consumption is reduced by 37.5 percent on average.

Quail: Using NVM write monitor to enable transparent wear-leveling

Emerging non-volatile memory (NVM) technologies promise persistence, byte-addressability, low power consumption and high density. The potential of NVM implies that it can improve persistence performance and availability for high-performance computing tasks in data centers. However, NVM suffers from limited write endurance; skewed writes can extremely curtail the lifetime of NVM. Although several wear-leveling algorithms have been proposed to address the wear-out problem, based on estimation of write counts, they come with limitations in accuracy and compatibility with existing hardware and softwares. In this paper, we propose several software-based ways of monitoring NVM writes and obtaining the write counts, which are more accurate and non-intrusive for existing programs. We compare our proposed monitoring approaches in the aspects of granularity and portability; we conduct extensive experiments to evaluate them and the results show that our proposed methods can obtain good accuracy with an affordable time overhead.

We demonstrate a flexible nonvolatile multilevel memory and artificial synaptic devices based on the Cu/P(VDF-TrFE)/Ni memtranstor which exhibits pronounced nonlinear magnetoelectric effects at room temperature. The states of the magnetoelectric voltage coefficient αE of the memtranstor are used to encode binary information. By applying selective electric-field pulses, the states of αE can be switched repeatedly among 2n states (n = 1, 2, 3) in a zero dc bias magnetic field. In addition, the magnetoelectric coefficient is used to act as synaptic weight, and the induced magnetoelectric voltage VME is regarded as postsynaptic potentials (excitatory or inhibitory). The artificial synaptic devices based on the Cu/P(VDF-TrFE)/Ni memtranstor display the long-term potentiation (depression) and spiking-time-dependent plasticity behaviors. The advantages of a simple structure, flexibility, multilevel, and self-biasing make the Cu/P(VDF-TrFE)/Ni organic memtranstor a promising candidate for applications in nonvolatile memory as well as artificial synaptic devices with low energy consumption.

Microcontroller units (MCUs) are often used in Internet of Things nodes that operate intermittently. Such nodes alternate active and inactive phases under strict energy constraints. Typically, the memory system has a significant impact on overall MCU energy consumption. Memory accesses and memory leakage power often dominate the consumption of active and inactive phases, respectively. Emerging Non-Volatile Memory (NVM) technologies have recently enabled the design of non-volatile MCUs that can significantly reduce energy consumption during inactive phases. However, replacing all memories with emerging NVMs is not necessarily the best solution, as it often results in dynamic power overhead during active phases. Instead, a hybrid memory architecture that combines volatile and non-volatile technologies is a promising alternative. However, designing hybrid memory MCUs is challenging because the technology that best fits a data segment depends on its access pattern during execution (e.g., program memory experiences mostly reads while the stack alternates reads and writes). For a given intermittent application, our goal is to find the best memory architecture based on a data mapping that takes advantage of the different properties of the available memory technologies. To this end, we present MemCork, a tool for hybrid memory architecture exploration in intermittent computing devices. Based on an instrumented execution on a technology-agnostic FPGA prototype, our tool exhaustively explores the possible data mapping and memory architecture combinations to find the most energy-efficient solution. We evaluate MemCork on two representative intermittent applications and find a customised memory architecture and data mapping that reduces energy consumption by up to 23% compared to a fully NVM solution.

As generative Artificial Intelligence (AI) models become increasingly integrated into software development workflows, understanding their efficiency and code quality is critical. This study offers a comprehensive comparison of three leading AI models—ChatGPT GPT-4-turbo, Claude Sonnet, and DeepSeek-V3—for automated code generation, focusing specifically on sorting algorithms. The models are evaluated across multiple metrics including execution time, memory usage, peak memory consumption, logical and physical file sizes, and code readability. Python implementations of Insertion Sort, Merge Sort, Quick Sort, and Heap Sort are generated by each model and benchmarked in a consistent Linux Docker environment. Results reveal that ChatGPT leads in overall efficiency, with the fastest average execution time, the lowest peak memory usage, and the highest readability scores. DeepSeek demonstrated competitive performance, especially in producing readable code, while Claude showed higher memory consumption and lower readability. This analysis provides practical insight into the trade-offs between code quality and system performance in AI-generated programming, offering valuable guidance for researchers and developers alike.

Research on sorting algorithms is a very core research field in computer science. Today, any advancement in sorting algorithms would lead to less time and space required to perform the sorting task. This paper discusses a newly proposed algorithm—‘ledger-based sorting algorithm’. It is basically an advancement to ‘counting sort’, but not exactly counting sort. The purpose of this paper is to reduce the time and space required for sorting when the numbers given to you belong to a particular range (0–n) and all of them are distinct. This paper also compares the newly proposed algorithm with insertion sort, bubble sort, selection sort, quick sort, merge sort and mainly counting sort through graphical time analysis of these algorithms. The paper especially compares counting sort algorithm with the proposed algorithm in terms of both time and space complexity.

The tree structure is notably popular for storage and indexing; however, tree-based sorting such as tree sort is rarely used in practice. Nevertheless, with the advent of byte-addressable storage (BAS), the tree structure captures our attention with its write-once property. This property aligns well with BAS's asymmetric read-write characteristics. In this paper, we seek to answer the question: Can tree-based sorting algorithms outperform existing algorithms in the hybrid DRAM-BAS system? To address this, first, we conduct a comprehensive study to assess the compatibility of existing sorting algorithms with such hybrid memory systems and explore the challenges. We then delve into various design dimensions of tree-sort algorithms which leads to an optimized variant, TSort. Finally, a comparative analysis is conducted among three different sets of sorting algorithms, including in-place sorts, external sorts, and tree-based sorts. The results indicate that TSort not only challenges the traditional negative perceptions of the tree structure in sorting but also exhibits excellent performance. It outperforms all other counterparts across diverse datasets, whether uniformly distributed or skewed, in most cases.

In this paper, we present a new parameterized parallel sort algorithm, called Round-Robin Partitioned (or RRP), for the message passing (shared-nothing) architecture. This is a parameterized sort algorithm because a parameter is provided which can be used to determine the amount of memory used and to allocate differing amounts of work to different sets of sites. We utilize pipelining to hide disk I/O time, exploit high degrees of parallelism at all phases, apply sampling to determine the partition key values and use less memory than previous known methods while repairing the minimum number of physical I/Os. The basic version of the RRP algorithm is simple in terms of coding and complexity. It does not require disk I/O parallelism or data prefetch within a single process. We develop an analytical model for our algorithm and compare our sort algorithm with four other classes of external parallel sort algorithms. The RRP algorithm are shown to be superior to the other algorithms for almost all configurations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In order to mitigate the problem of the memory wall, various emerging nonvolatile memory (NVM) technologies have been proposed to replace the traditional ones. These emerging NVMs include spin torque transfer random access memory, PCRAM, resistive random access memory, racetrack memory, etc. Compared to traditional memory technologies, they have the advantages of near-zero standby power, high storage density and nonvolatility, which make them competitive for future memory hierarchy design. However, it is inefficient to directly apply these NVMs in existing memory architectures. On the one hand, these NVMs have their own limitations, such as long write latency, high write energy, limited write numbers, etc. Thus, proper architecture modification is required to adopt them into the traditional memory hierarchy. On the other hand, the unique features of these NVMs allow new memory architectures in memory subsystems and also introduce new challenges to be solved at the same time. In this paper, we not only review various emerging NVMs but also study typical related work on these topics to investigate their implications for memory architecture design.

Large-capacity memory system allows big data applications to load as much data as possible for in-memory processing, which improves application performance. However, DRAM faces both scalability and energy challenges due to its inherent charging mechanism. Thus, DRAM-based memory system incurs excessive cost to meet both capacity and energy requirements for the emerging big data workloads. Fortunately, non-volatile memories(NVMs) are emerging with the advanced features of better scalability and lower power leakage. Integrating NVMs into main memory is non-trivial as NVMs have a few weakness, such as asymmetric read and write latency and power. Designing memory system comprising both DRAM and NVMs requires to understand the memory access behaviors of big data applications. In this paper, we first investigate the memory access patterns of both typical big data workloads and traditional parallel workloads. By doing so, we show the read/write intensity as well as temporal/spatial locality of big data workloads. We then replay memory access traces of big data applications to DRAM simulator and PCM simulator, respectively. We explore design implications of hybrid memory comprising DRAM and PCM.