An Efficient Stabilization Process for Analog Fractionally Spaced Equalizers

Clock and data recovery (CDR) circuit in general, plays a vital role for serial-link communication in multi-module based System on chip (SOC). It uses a high frequency clock to handle high data rate, which results in high dynamic power consumption. In order to reduce the high dynamic power consumption, the proposed design works at the one-eighth frequency of the received data rate and presents a novel digital octa-rate clock and data recovery circuit as an optimal solution. The octa-rate CDR circuit consists of 16-phases generator, delay line controller, an octa-rate early-late type phase detector and digitally controlled delay line. The purpose of delay line controller is to provide sufficient delay in digitally controlled delay line. It is observed from literature that the existing delay line controller is realized by using combinational circuit which is not providing sufficient delay. Hence, in this work we introduced Finite State Machine (FSM) based delay line controller to provide sufficient delay. In order to reduce dynamic power consumption, a novel octa-rate CDR circuit has been realized using Xilinx ISE 13.2 and implemented on Vertex-5 FPGA target device for real time verification. Corresponding results shows a significant dynamic power reduction.

Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable to predict the rate of occasional detection errors and the loss of synchronization due to the non-ideal operation of such circuits. In high-speed data networks, the bit-error-rate specification on the system can be very stringent, i.e., 10/sup -14/. It is not feasible to predict such error rates with straightforward, simulation based, approaches. This work introduces a stochastic model and an efficient, analysis-based, non-Monte-Carlo method for performance evaluation of digital data and clock recovery circuits. The analyzed circuit is modeled as finite state machines with inputs described as functions on a Markov chain state-space. System performance measures, such as probability of bit errors and rate of synchronization loss, can be evaluated through the analysis of a larger resulting Markov system. A dedicated multi-grid method is used to solve the very large associated linear systems. The method is illustrated on a real industrial clock-recovery circuit design.

Phase-locked loop (PLL) based clock and data recovery (CDR) circuits use a 2x-oversampling (2XO) of the incoming non-return to zero (NRZ) data stream to recover the data. As an extension of the idea, 3x-oversampling (3XO) CDR circuits provide improved performance in the presence of total asymmetric jitter. This paper presents an overview of the oversampling CDR circuits with an emphasis on digital architectures. These include, but are not limited to, the 3XO jitter-tolerant variable-interval 3XO architecture, the 3XO eye-tracking architecture, and the blind oversampling architecture. We propose a modified architecture that utilizes multiple rotating phases to improve the performance of the 3XO eye-tracking architecture

A 5-Gb/s clock and data recovery (CDR) circuit, incorporating 625 MHz interpolating voltage-controlled oscillators (VCO) and four-phase 1/8-rate phase detectors (PD), is demonstrated. The PD provides a linear characteristic that is proportional to the phase difference between the four-phase clocks and the input 5-Gb/s data, and hence produces four-demultiplexed 1.25-Gb/s outputs. The VCO is designed as a four-stage differential ring oscillator, employing the half-rate clock technique so that it can provide 1/8-rate clocks with delay interpolation. Test chips are fabricated in a 0.25 /spl mu/m CMOS technology. The whole chip occupies an area of 1.7/spl times/1.4 mm/sup 2/ together with on-chip low pass filters, i.e., two 16 pF capacitors and 63 k/spl Omega/ resistors. Post-layout simulations show that the recovered data output exhibits 40ps/sub p-p/ jitter characteristic for 2/sup 23/-1 PRBS serial NRZ input. The chip core dissipates 130 mW from a single 2.5 V supply.

In this paper, a novel wavelet packet division multiplexing (WPDM) system based on Fractionally Spaced Equalizers (FSE) and Maximum Likelihood (ML) algorithm is studied for multipath fading channels. New discrete wavelet packet transform structure based on FSE, which uses Least Mean Square (LMS) algorithm and ML detecting algorithm, are the two novel aspects of the presented system. It is demonstrated by simulation results that the FSE method is superior to the Zero-Forcing equalizers (ZFE) method in performance and the FSE-WPDM scheme can provide greater immunity to multipath fading channels and AWGN than the FSE-OFDM scheme.

This paper presents a programmable half-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O links. The CDR is implemented in TSMC 28nm high-k metal-gate CMOS technology and covers a continuous range of data rates from 2.5Gb/s to 12.5Gb/s. The higher data rate is achieved by demultiplexing and decimating the sampled data in order for the subsequent circuit to operate at a much lower speed. The CDR is able to track maximum frequency deviation of ±286.78 ppm between the incoming data and the local reference clock at 12.5Gb/s. The CDR occupies a chip area of 18700um2 and consumes 30.30mW of power at 12.5Gb/s.

In the digital transmission system, an efficient fractionally-spaced equalizer (FSE) for blind equalization based on modified constant modulus algorithm (MCMA) and phase locked loop (PLL) is proposed. Comparing with conventional FSE based on famous CMA, the proposed algorithm has not only lower steady-state mean square error and faster convergence rate but also the ability to recover carrier phase rotation. The efficiency of the method is proved by computer simulation.

A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18- μm CMOS process, and a bit error rate of less than 10-12 was achieved for a data rate up to 5.8 Gb/s using a 231 - 1 pseudorandom binary-sequence input.

We introduce a bit-error-rate (BER) estimation technique for high-speed serial links, which utilizes the jitter spectral information extracted from the transmitted data and some key characteristics of the clock and data recovery (CDR) circuit in the receiver. In addition to offering insight into both the behavior of the CDR loop and the contribution of the jitter to the BER, the estimation technique can be used to accelerate the jitter tolerance test by eliminating the conventional BER measurement process. We will discuss two different versions of the estimation technique: one for use with linear CDR circuits and the other for non-linear CDR circuits. Experimental results comparing the estimated BER and the measured BER demonstrate the high accuracy of the proposed technique.

This paper presents a power and area efficient approach to embed a continuous-time linear equalizer (CTLE) within a clock and data recovery (CDR) circuit implemented in 65-nm CMOS. The merged equalizer/CDR circuit achieves full-rate operation up to 28 Gb/s while drawing 104 mA from a 1-V supply and occupying 0.33 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Current-mode-logic (CML) circuits with shunt peaking loads using customized differential pair layout are used to maximize circuit bandwidth. To minimize the area penalty, differential stacked spiral inductors (DSSIs) are employed extensively. A novel and practical methodology is introduced for designing DSSIs based on single-layer inductors provided in foundry process design kits (PDK). The DSSI design increases the inductance density by over 3 times and the self-resonance frequency by 20% compared to standard single-layer inductors in the PDK. The measured BER of the recovered data by the CDR is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> at 27 Gb/s for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> -1 400 mV PP pseudo-random binary sequence (PRBS) as input data. The measured rms jitter of the recovered clock and data are 1.0 and 2.6 ps, respectively. The CDR is able to lock to inputs ranging from 26 to 28 Gb/s with 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> -1 PRBS pattern. Measurement results show that with the equalizer enabled, the CDR can recover a 26-Gb/s 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1 PRBS data with BER ≤ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> after a channel with 9-dB loss at 13 GHz.

This paper describes a clock and data recovery circuit that operates at 2.5Gb/s in a 1.8V 0.18um digital CMOS technology. It is a main part of the receive path in a fully integrated CMOS SerDes transceiver. A frequency-aided PLL-based dual-loop architecture is adopted. To suppress the noise, a ring oscillator composed of differential buffer delay stage is introduced that employs some technique to lower the gain. A special data-triggered phase/frequency detector is also described. A transistor-level simulation shows the overall lock behavior.

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 μm CMOS process and occupies an active area of 0.2 × 0.32 mm2. The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.

A 10 Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. In 0.18 /spl mu/m CMOS technology, the circuit exhibits 1.43 GHz capture range and 0.8 ps rms jitter with length 2/sup 23/ PRBS. The power dissipation is 91 mW from a 1.8 V supply.

A clock and data recovery circuit for a T1 network is described. A fully integrated PLL extracts the carrier signal embedded in the data. Two tri'mming DAC's simultaneously bring the VCO center frequency and the PLL closed-loop bandwidth to their specified values. A triple sampler captures the jittering data and aligns them with the recovered clock. The input jitter tolerance of this circuit is three times more than previously reported PLL-based circuits