An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis

As semiconductor technology continues to advance at an unprecedented pace, the integration of smaller and more densely packed transistors on silicon wafers has ushered in an era of unrivaled power and energy efficiency. However, this rapid advancement also introduces a significant and growing challenge: the increasing problem of process variation. Variations in manufacturing processes, device characteristics, and environmental conditions can result in large changes to performance and reliability for integrated circuits (IC). These variations introduce substantial hurdles to achieving predictable timing performance in modern electronic systems. This work delves into the multifaceted issue of process variation and presents a novel, variation-aware clock tree synthesis methodology (Var-CTS) to address that variation. Var-CTS is used during the initial synthesis stage of physical design to improve the statistical worst case timing. Using a timing library characterized for variation, the methodology uses variation-aware merging regions for skew that improve timing and resilience against variation. Building up to the variation-aware clock tree synthesis, two studies for clock slew and wiring type are performed and one methodology considering bounded clock tree synthesis is presented. The first study explores the effects of slew on clock power and timing. The study shows that slew constraint manipulation can improve power consumption while maintaining high-performance operation. A study of a uniquely fundamental wiring type is performed that can improve routing density, an important aspect for reducing wire variations during manufacturing. The implemented wiring type is determined to have positive effects on both the timing of the implemented clock trees with the added consideration of routing density. A bounded skew and slew merging region methodology for clock tree synthesis is presented to improve performance of the implemented clock tree. The methodology shows improvement over previous research due to multi-constraint merging regions during the clock tree synthesis merging process. Finally, the variation-aware clock tree synthesis methodology is presented. Results from Monte Carlo-based simulations show how including statistical timing information in the clock tree synthesis methodology improves the final statistical worst-case skew variation of a high-performance clock tree.

Modelling uncertainty in multi-cycle latch paths presents unique challenges due to variations in voltage supply and noise-induced timing fluctuations. Traditional Static Timing Analysis (STA) applies uniform single and half-cycle uncertainties, which proves insufficient for complex multi-cycle paths - particularly those involving latches [3]. Jitter and high-frequency noise impact multi-cycle paths differently from single-cycle paths, exacerbating inaccuracies. Existing tools like Primetime lack direct mechanisms to manage these pathspecific uncertainties. Primetime Cycle-Dependent Uncertainty (cycle_value) feature addresses these limitations by enabling cycle-specific uncertainty modelling. Designers can assign distinct uncertainty values to different cycle counts, enhancing accuracy in noise and jitter representation across multiple cycles. This feature further supports latch path modelling by incorporating transparency window uncertainties, aiding precise timing analysis for data arrival, cross-talk, and slack assessment. In Nvidia designs, the cycle_value feature has been evaluated and integrated into established timing flows. It works alongside traditional single-cycle uncertainties to maintain consistent, reliable modelling across diverse design scenarios. This advancement empowers designers to handle multi-cycle paths with greater precision, improving overall design robustness and performance predictability.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.

Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult. Based on that observation, in this paper, we present a novel clock tree design style, called type-matching clock tree, to ensure that the logic gates at the same level are in the same type. We prove that any clock control logic can always be transformed to our type-matching clock tree. Then, based on the idea of type-matching clock tree, we propose a zero skew gated clock tree synthesis algorithm. Compared with the industry- strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.

Buered clock tree synthesis (CTS) is increasingly critical as VLSI technology continually scales down. Many researches have been done on this topic due to its key role in CTS, but current approaches either lack the obstacle-avoiding functionality or lead to large clock latency and/or skew. This paper presents a new obstacle-avoiding CTS approach with separate clock tree construction and buer insertion stages based on an integral view to explore the global optimization space. Aiming at skew optimization under constraints of slew and obstacles, our CTS approach features the clock tree construction stage with the obstacle-aware topology generation algorithm called OBB, balanced insertion of candidate buer positions, and a fast heuristic buer insertion algorithm. Experimental results show the eectiveness of our CTS approach with significantly improved skew and latency than [6] by 46% and 63% on average, and 15.3% reduction in skew than [5]. Our OBB heuristic obtains 36% improvement in skew than the classic balanced bipartition algorithm (BB) in [10].

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal which incurs a high clock routing overhead. Besides, the clock tree of an SFQ circuit requires the insertion of a clock splitter cell at every tree branching point which renders the conventional design flow of placement followed by clock tree synthesis ineffective to obtain a high quality clock tree with low clock skew. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by clock tree synthesis and clock splitter insertion, and then performs a second stage of global placement to re-place both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is re-synthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. In addition, the total wirelength of data signals and clock signal is optimized concurrently. After legalizing the placement of all cells, our placement refinement method can be run to further reduce the clock skew. Compared with the previous state-of-the-art work, on average we can reduce the total half-perimeter wirelength and clock skew by 9% and 31%. respectively.

Clock trees can be constructed based on static arrival time constraints or dynamic implied skew constraints. Dynamic implied skew constraints allow the full timing margins to be utilized. However, the dynamic skew constraints require a high run-time complexity to be evaluated. In contrast, static arrival time constraints are more restrictive but can be evaluated in constant time. Consequently, there is a tradeoff between timing margin utilization and run-time. In this paper, a scalable clock tree synthesis (CTS) framework is proposed for the construction of low-cost useful skew trees (USTs) with high timing quality. The scalability is based on combining the use of arrival time constraints with virtual minimum and maximum delay offsets, which facilitates that a pair of smaller subtrees can be joined into a larger subtree in constant time. The ability to quickly join subtrees is leveraged to perform a high degree of solution space exploration, which translates into the construction of USTs with low-cost. In particular, clock trees with various routing tree topologies, buffer tree topologies, buffer sizes, and stem wire lengths are explored. Moreover, the arrival time constraints are specified with the objective of being the least restrictive to reduce cost. Furthermore, the constraints are respecified throughout the tree construction process using a slack graph (SG) to expose additional timing margins. The high timing quality is obtained by seamlessly integrating arbitrary timing models using the SG. Finally, the proposed CTS framework is integrated with a clock tree optimization framework to demonstrate that the constructed USTs are capable of meeting timing constraints under the influence of on-chip variations.

The impact of parameter variations on timing due to process variations has become significant in recent years. In this paper, we present a statistical timing analysis (STA) framework with quadratic gate delay models that also captures spatial correlations. Our technique does not make any assumption about the distribution of the parameter variations, gate delays, and arrival times. We propose a Taylor-series expansion-based quadratic representation of gate delays and arrival times which are able to effectively capture the nonlinear dependencies that arise due to increasing parameter variations. In order to reduce the computational complexity introduced due to quadratic modeling during STA, we also propose an efficient linear modeling driven quadratic STA scheme. We ran two sets of experiments assuming the global parameters to have uniform and Gaussian distributions, respectively. On an average, the quadratic STA scheme had 20.5times speedup in runtime as compared to Monte Carlo simulations with an rms error of 0.00135 units between the two timing cummulative density functions (CDFs). The linear modeling driven quadratic STA scheme had 51.5times speedup in runtime as compared to Monte Carlo simulations with an rms error of 0.0015 units between the two CDFs. Our proposed technique is generic and can be applied to arbitrary variations in the underlying parameters under any spatial correlation model

Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock tuning. Existing design approaches for post-silicon-tunable (PST) clock-tree synthesis usually insert a PST clock buffer for each flip-flop or put PST clock buffers across an entire level of a clock-tree. This can cause significant over-design and long tuning time. In this paper, we propose to insert PST clock buffers at both internal and leaf nodes of a clock-tree and use a bottom-up algorithm to reduce the number of candidate PST clock buffer locations. We then provide two statistical-timing-driven optimization algorithms to reduce the hardware cost of a PST clock-tree. Experimental results on ISCAS89 benchmark circuits show that our algorithms achieve up to a 90% area or a 90% number of tunable clock buffer reductions compared to existing design methods.

Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock tuning. Existing design approaches for post-silicon-tunable (PST) clock-tree synthesis usually insert a PST clock buffer for each flip-flop or put PST clock buffers across an entire level of a clock-tree. This can cause significant over-design and long tuning time. In this paper, we propose to insert PST clock buffers at both internal and leaf nodes of a clock-tree and use a bottom-up algorithm to reduce the number of candidate PST clock buffer locations. We then provide two statistical-timing-driven optimization algorithms to reduce the hardware cost of a PST clock-tree. Experimental results on ISCAS89 benchmark circuits show that our algorithms achieve up to a 90% area or a 90% number of tunable clock buffer reductions compared to existing design methods.

Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.

Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional works that handle this problem with clock routing or buffer sizing, this paper proposes a novel register clustering algorithm in generating the leaf level topology of the clock tree to reduce the power consumption. Aiming to guarantee the stability of our register clustering algorithm, an effective initialization algorithm called “K-Splitting” and a “Pseudo Center” technology are developed. Meanwhile, a buffer allocation algorithm is proposed to satisfy the slew constraints within the clusters at a minimum cost of power consumption. We implement the clock tree synthesis (CTS) flow in [2] to test our approach on ISPD'10 benchmark circuits. Experimental results show that our register clustering algorithm achieves a 29.0% reduction in power consumption as well as a 5.7% reduction in max latency without affecting the clock skew. Moreover, the total runtime of the CTS flow with our register clustering algorithm is significantly reduced by 87.3%.

Static timing analysis for modeling QoS in networks-on-chip

An accurate prediction of circuit delay distribution is essential to verify the timing closure of digital circuits and to estimate the parametric yield. In the presence of process variations, the most accurate technique for circuit delay prediction is using Monte Carlo simulations. However, to get an accurate estimate, a large number of Monte Carlo simulations are required which is infeasible in the case of large circuits. Although statistical timing analysis techniques are widely used to predict the circuit delay distribution in a reasonable run time, the standard deviation of circuit delay is often inaccurate. In this work, an efficient technique for circuit delay prediction using limited number of Monte Carlo simulations is proposed. This is done using the concept of Bayesian inference with the results from statistical timing analysis as the prior information. The results indicate that combining statistical timing analysis along with limited number of Monte Carlo simulations increases the accuracy of prediction of circuit delay variance. The number of Monte Carlo simulations can be decided based on the accuracy requirements or run time constraints.

3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology generation, with reduced runtime. In addition, a postorder traversal based layer embedding (PTLE) strategy is adopted for determining the embedding layer of internal nodes with minimal TSV usages. Experimental results show that the proposed method achieves 32% and 82% runtime reduction on ISPD2009 and IBM benchmarks respectively compared with the state-of-the-art 3D work. Besides, the TSV count is also reduced by 46% on ISPD2009 benchmarks.